Net to Net

Although system designers tend to use fewer traces to minimize costs, this usually results in tightly packed traces. Tightly spaced traces have more crosstalk and have power handling capability. Depending on the design, tradeoffs may be necessary to accommodate system requirements. The rule of thumb is using 3W-rule to provide a clearance W when the width of each trace is W. However, the clearance W needs to be adjusted for crosstalk and EMI consideration. This item checks whether a specified clearance requirement for the net is satisfied. For example, a clearance among Data Bus and that among Clock are specified differently. By specifying a reference net and a target net, it checks for clearance between traces, pads and vias not only on the same layer but also on adjacent layers.

• Auto Net to Net Combination: Generate combination pair of selected net group.
• Item: Input item name.
• 1st Net: specify 1st net (reference).
• 2nd Net: specify 2nd net (target net).
• Type: Define separation measure base.
  • Value: The clearance value in Strip Clearance, Microstrip Clearance, Strip Clearance with Pad/Via and Microstrip Clearance with Pad/Via are considered as Separation Value.
  • Width: The value in Strip Clearance, Microstrip Clearance, Strip Clearance with Pad/Via and Microstrip Clearance with Pad/Via are considered as multiple of Pattern Width.
• Strip Clearance: Enter trace-to-trace clearance for stripline (traces on inner signal layers).
• Microstrip Clearance: Enter trace-to-trace clearance for microstrips (traces on top and bottom layers).
• Stripline Clearance with Pad/Via: Enter trace-to-pad or trace-to-via clearance for stripline.
• Microstrip Clearance with Pad/Via: Enter trace-to-pad or trace-to-via clearance for microstrips.
• Net Exception: Check clearance between 1st Net group and all other signals exclude 2nd Net group.
• L1 Clearance: Enter clearances from the reference layer to the one layer above and below.
• L2 Clearance: Enter clearances from the reference layer to the two layers above and below.
• Pin Escape: Enter a radius of circular region around pins to be excluded for the rule check.
• Area Layer: Select the artwork layer to be checked. PollEx DFE recognizes check areas defined by polygon or polyline.
• Area Clearance: Enter a clearance to the region that is defined in Area Layer.
• Component Keep IN/OUT: Define the test region. For example, you can test inside or outside the breakout region of CPU with different test values.
• Component Keep in/out:
  • Component Group: Select the required component group which is used for defining the test region.
  • Region: Define the required test region.
    • IN: Test inside of the breakout region of target component.
    • OUT: Test outside of the breakout region of target component.
• Range (COC+distance): Enter the distance value to define breakout range. The COC (Component Overlap Check) plus this distance value is considered the test range.
• Target Layer: Select the required test layer.
  • All Layer: Test all layers.
  • Component Place Layer: Test only the component placement layer.
  • GND Net: DFE skip to check if ground net is existing between two target nets.
  • Width base item: Only the item listed here will be affected by option ⑤.

    
    
    Figure 1.

As an example, the table below shows clearance differences varied by voltages. This sample table is for illustration purpose only and should not be adopted in an actual design.