List of API Examples

This file contains an example for the use of the Analog Waveform library access functions.

The used functions allow to parse spice simulation results and to retrieve the contained data.

The comments in the example code give more explanations on the performed API function calls.

Add a new main menu entry to loop over all objects loaded to the Cone window and automatically load all direct connections between objects.

Create dummy objects and associate arbitrary file positions with these objects. Now any position in a source file can be highlighted.

Small transistor example.

Update the displayed name of all modules to show additional information.

Analyze the connectivity of a blackbox instance and try to arrange the pins on the left or right side depending on the connectivity.

Report the top 5 resistance values in the selected RC network. Usage:

This is a prototype implementation of a Cone window annotation feature. To access this feature the main menu is extended by an Annotate Cone button.

The Start Annotation menu entry will activate the annotation mode and disables the normal mouse actions like zoom, double-click, etc. Now simple elements like rectangles, circles, lines and text boxes can be added on top of the schematic.

Annotation items can be moved or deleted using the corresponding menu entry. The Clear Annotation menu entry will remove all created annotation objects. The End Annotation entry will switch back to normal mode an re-install all normal mouse bindings. This will also remove all created annotation objects.

Assign a built-in symbol shape to a loaded primitive. The first character of the instance name defines the symbol type.

Open a design database, automatically map all symbols for all database cells matching by name, render the schematic for each module and export the schematic as a Skill file.

Read a System Verilog design and export the created netlist as a structural Verilog netlist.

Export the schematic as Skill in batch mode using starsh.

Call post process operators to beautify the schematic.

Display the contents of a Cadence cds.lib file.

Fill the database with the bus85 example design. The bus85.tcl example refers to the bus85prim.sp spice source. The bus85prim.sym Symbol library fits to the bus85.tcl example.

Use this userware to load the bus85.tcl without transistors.

Skeleton that can be used to create a shared object that can be loaded into the *Vision tools to register new Tcl Object Commands.

Add a main menu entry to calculate the estimated chip area.

Add a comment to the top module with the total area.

A text report with details about the chip area consumption can be created.

Calculate new width based on the product of m and w.

Report the pin-to-pin resistance for two given pins on the same net without opening the Parasitic window. Select two pins on the same net and access this function from the extended Popup menu.

Userware example for the ClockTree API. Do additional CDC checks.

Loop over all output pins of all instances of the given start cell list and check that each output pin only connects to one instance of the given IP cell list.

Find and highlight io devices matching the given model name pattern.

Loop over all signals and check if a signal has more than one driver.

Loop over all PMOS and NMOS transistors and check if their bulks are connected to power and ground respectively. If not, the transistor is reported in the Mem window.

Loop over all signals and check if a signal has no driver.

Find signals that connect transistors in a low voltage zone with transistors in a high voltage zone.

Extract the clock tree structure of the loaded design.

Usage: - Right click on an input port (e.g. CLK) and invoke - "Userware→Clock Tree" from the context menu. - Now switch to the Cone window to see the result.

Traverse Design and collect statistics.

Color nets in the loaded database.

Example Tcl script to compile all HDL design files into an in-memory (ZDB) database to be used with the Vision SDT platform. In the binary directory (linux64 or win64) of the Vision platform package you can find the starsh binary. This is a Tcl shell extended by all HDL parsers provided by the Vision platform. Either use the option -help to get a list of all possible options or see doc/parser/*parser.html for a more detailed description of the parser options.

Compute and display statistics about the devices used in the design.

Compute and display statistics about the design hierarchy, e.g. number of instances of each cell, depth of hierarchical modules, etc. The statistics can also be exported as a CSV file.

The plugin script can also be run in batch mode via: starsh hierarchyStatistics.tcl -batch ZDB_FILE OUTPUT_FILE

Compute and display the differences of the currently loaded database and a binary database (.zdb file). Can be run directly from the command line using the command line options -userware3 diff.tcl db1.zdb db2.zdb.

API example how to use the Cone extraction API: extract the logic cone or path between a start node and several targets.

Add a main menu entry to highlight complete or empty modules loaded in the Cone window in different colors.

Configure which attributes are displayed at *MOS devices.

Userware to flag cells as clocked cells and ports of clocked cells as the clock ports.

Extend the Popup menu and add a new entry to disconnect the connected net and connect a constant 1 or 0 to the pin. It is also possible to restore the original connectivity.

Extend the popup menu and add an entry to add all direct connections between two selected instance in the Cone window.

Convert symbols from slib format to zdb and show all symbols.

Add a main menu entry to collect information about all coupled K-objects and load all instances to the Mem window.

Coupled instances can be displayed in the Cone window including all connected R, C or L devices. If option Full LRC is set the corresponding R and C to the L are loaded into the cone, too.

Coupled instances can be grouped into a new hierarchy.

Report coupling Cs in the Mem window.

Create and fill a binary database using the C-Level API.

Create and use OIDs the C-Level API.

This example shows how to use the waveform parser to - read a DC analysis result file - traverse all curves defined in this file - create value attributes in the schematic from this data

This example shows how to use the waveform parser to - read a transient analysis result file - traverse all curves defined in this file - create value attributes in the schematic from this data

Create and fill flat binary database using the C-Level API.

Create a design overview report of the loaded design either in HTML or ASCII text format. This example can easily be extended to create an other output format.

The HTML pages contain many typical information about the design, such as: module and submodule names with their instantiations, schematics, input/output/inout ports, clocked elements, all with the places of definition in the source files. Furthermore Operator types and Primitive functions are printed with the number of their occurrences.

Alternately you can create the same information in text files - without connecting links, of course.

In addition to the schematics in HTML, linked pdf files are generated; they have better zoom view options than the former.

DIRECTIONS:

Load all Spice files in a given folder and create a PNG image of each sub-circuit.

Loop over spice files; read each spice file (by calling zspice <options>) and then load each sub-circuit into the Schem window and print it to postscript.

Terminology: ZDB uses the Verilog name Module for a Spice "sub-circuit" and the name Primitive for a Spice "model".

Print all attributes of all instances to a text file.

Create a list of instance names with their corresponding page and sector. If the instance has an attribute named 'PartValue' then the value of this attribute is added to the created instance list.

Create portbuses and netbuses from single bit ports and nets.

Create portbuses and netbuses from single bit ports and nets.

The script can be used as a template for creating special purpose versions. The hard coded pattern for collecting simple buses may need modifications. Currently the pattern for collecting single bits matches simple names like A[1], B{1}, C_1_ or A1.

Foreach module all nets are examined. If the name (e.g. BUS[77]) matches a pattern containing a basename (e.g. BUS), some letters preceding the bitsubscript (e.g. [) and some trailing letters (e.g. ]) this triplet is used as an index identifying the bus. All bitsubscripts (e.g. 77) are collected and sorted in a list. After all subscripts are collected, a netBus or portBus is created. For PortBuses there are no "gaps" in the bitsubscripts allowed. If a net is already member of a bus the bitsubscript list is cleared to mark the bus as already bundled.

This script can be used to create a Quartus project.

A script that can be used to generate a zdb binfile of a timing netlist from TimeQuest.

This script can be loaded as a Userware in RTLvision PRO or as a script in the batch tool starsh. In both cases a zdb binfile is created based on the netlist in the Tcl file <PROJECT>.rtlvision.tcl.

Create a new top block around all instances in the old top.

Create symbols for cells with UNISIM-style names.

The function is activated by the new main menu entry Userware > UNISIM Symbols.

Extend the popup menu with an entry Show Liberty to cross-probe from the schematic to Liberty source code.

API example of demo/spice/csim90 spice files.

This Userware binds a special hotkey to toggle the visibility of all netnames.

Example code for doc/tutorial/guiCustomization.html

Example code for doc/tutorial/guiCustomization.html

Example code for doc/tutorial/guiCustomization.html

Example code for doc/tutorial/guiCustomization.html

Example code for doc/tutorial/guiCustomization.html

Compare two ZDBs. Differences are printed to STDOUT. If there are no differences, the script terminates with exit code 0, otherwise with exit code 1.

Usage:

Internal SPEF debugging.

Delete all netBus information in the loaded database.

Extend the Popup menu to delete selected objects from the loaded database.

Extend the Popup menu to show all connections of a net/signal.

A demo plugin to demonstrate all features of the plugin API:

Display a "Design Histogram" of the loaded design database.

Detect and highlight any FF/latches (with specific std cell name pattern) that is directly connected to the input ports (directly driven by input ports without any buffers/inverters).

Detect and highlight any FF/latches (with specific std cell name pattern) that is directly connected to the input ports (directly driven by input ports without any buffers/inverters).

Add comments from a file to the netlist.

This example script demonstrates how to display path extraction results generated by the extract C demo and stored as database root attributes in the Cone window.

Display the voltages in the given file at the nets.

Do additional CDC checks. The user can specify that input ports are in sync with a specific clock.

Analyze a given ZDB and produce the following design metrics for each design (top level module):

Dump hierarchy information to a text file.

Right click on a hierarchical instance or module to invoke the Dump Hierarchy function from the Userware Popup menu. This function will write hierarchy information starting from the selected object.

From the Userware main menu the Dump Hierarchy Tree function can be used to dump the hierarchy tree for each top module.

Add a main menu entry to loop over all modules and dump the I/O ports to a text file.

Dump the contents of the zdb database into an ASCII text file. This example do not need Tcl and can be used as a reference how to access the ZDB structures.

Change all W/L attributes and update the Spice file.

This plugin extends the Popup menu to add comments to the selected object.

From the extended main menu a report can be displayed or saved as a text file.

Also, all objects with a comment can be loaded to the Mem window.

The plugin also lets the user toggle the display of comments at nets in the schematic view.

Allow simple ECO changes.

This userware assist the user to do ECO changes. The Popup menu is extended to perform the following operations on insts/pins:

For each operation a string with the performed action is printed to the Console window. Instead of this text a DC-script could be created to perform the ECO action on the netlist.

Add various ERC checks to the main menu.

Usage example for ERC:check02 "Floating Gates".

C implementation of the fillflat Userware. This example script demonstrates how to use the flat tree creation compiled as a shared library in the starsh.

C implementation of the floatingNodes Userware. This example script demonstrates how to use the userware extension compiled as a shared library in the *Vision GUI as well as in the starsh.

Message and debug C-Level API.

Shows the usage of the Gui Wave API functions and the extension of a wave database via the TCL API.

Read the side file 'excludeCell.txt' and match the name patterns against the loaded database to flag cells exclude from the cone extraction.

Expand the connectivity of devices in the Cone window excluding all the MOS devices that are connected to the net by the 'gate' pin.

Extend the popup menu and add an entry to expand the first logic level of all selected hierarchical instance in the Cone window.

Since the binlib file format becomes incompatible if the database structure changes here are two scripts that can be used to migrate the contents of a compiled binlib to a new binlib version.

Run the old version of *Vision to export the binlib to Tcl:

Run the new version of *Vision to import the Tcl and save a new version of the binlib:

Export a mangled/obfuscated version (stripped attributes, replaced names) of the currently displayed module or the whole database.

This script contains procedures to query netlist information from the Quartus database and writes out $db load …​ statements.

Export the schematic as EDIF.

Extract logic cloud from all given start points to all clocked elements and load the result to the Cone window. Flip-flops belonging together are lined up in columns and get the same color.

Extract a path using the C-Level API.

C implementation of the fillflat Userware. This example script demonstrates how to fill flat data compiled as a shared library in the starsh.

This script can be used to filter parasitic elements of the RC network displayed in the Parasitic window. Sometimes the RC network even for a single net is too complicated and therefore when viewed for multiple nets, it can be very complicated to for debugging and visualization.

This script enables the user to:

Add a main menu entry to find all blackbox cells in the loaded database and show the result in the Mem window.

Find all instances of clocked cells and check the nets connected to the clock and reset pins.

Traverse the design hierarchy tree for all Rs, check the resistance value, and collect the objects bigger than the defined threshold value. The result is stored in the Mem window.

Find duplicate sub-circuits loaded from a SPICE netlist.

Loop over all nets/signals and count the number of pins for each net/signal. All nets/signals with exactly one pin are stored in the Mem window.

Loop over all instances and find floating gates. The result is stored in the Mem window.

Loop over all signals and report signals that have no driver. Also loop over all primitive instance pins and report unconnected inputs.

Loop over the database and find floating/dangling member nets in netbuses. Results are displayed in the Mem window.

Loop over all nets/signals and count the number of pins for each net/signal. All nets/signals with exactly one pin are stored in the Mem window.

Loop over all signals report signals that do not drive anything.

Add a main menu entry to find all guessed supply nets in the loaded database and show the result in the Mem window.

The heavyCR procedure loops over all C or R and checks each value (capacitance or resistance) and collects the 10 objects with the biggest values. The 10 biggest Cs and 10 biggest Rs are stored in the Mem window. heavyCR is the tree-based version.

The heavyCR procedure loops over all C or R and checks each value (capacitance or resistance) and collects the 10 objects with the biggest values. The 10 biggest Cs and 10 biggest Rs are stored in the Mem window. heavyCRt is the tree-based version.

Loop over all signals and count the number of pins for each signal. The 10 biggest signals are stored in the Mem window.

Find all instances without SDF info. Load to mem or mark them.

Based on a given list of cell name patterns create an output file to list all instantiation paths to cells matching the given pattern list.

Extract and show the longest path between two selected objects.

Features:

Find parasitic nets with no driver. A driver is either:

Find all paths between the output pins of a given start module instance and any pin of a given target module instance.

Read an input file that contains cell names and pin names. Then a path search is performed and the name of the first reachable clocked cell is dumped into an output file.

Find paths from all nets of a given block to all IP blocks (flag undefined).

Flag all nodes that matches one of the given patterns with a power, negpower or ground flag to get a more readable schematic.

Read a side file that contains pairs of FF pins. The task of this userware is to find paths with reconvergent logic between these pins. The first column in the file is used as the start pin the second column is used as the target pin.

Search for transistor devices by name. The device might be moved to a new hierarchy created by the 'Recognize Gate' feature.

Rename net objects to follow the Cadence Virtuoso bus naming semantic.

Adjust instance and net names to satisfy the Cadence Virtuoso namespace rules. - Instances cannot contain a dot character. - Scalar net names and netbus names share the same namespace.

Flag all modules listed in the provided side file as a leaf cell.

Flat all instances of a given module. For the simple case of only one hierarchy '$db oper expand' may be an simpler approach.

Example Tcl script that uses ZDB API commands to flatten the design in the given binary ZDB file and write out a structural Verilog netlist of the flattened database. Usage: starsh flatDesign.tcl design.zdb design.v

C implementation of the floatingNodes Userware. This example script demonstrates how to use the userware extension compiled as a shared library in the *Vision GUI as well as in the starsh.

Overwrite existing cell symbols with symbols in the specified symbol library file.

Create nice symbol shapes for all LUT cells.

Extract FSM information copied from the parse tree to the netlist database and display FSMs using a graphical and a table view.

Functions to print parsed data.

Read a text file containing names of hierarchical instances. For all nets inside these sub-circuits the RC network will be loaded to the Parasitic window and a Spice netlist is created.

Example code to extract the DEF string for the built-in symbol shapes.

Group the contents of the Cone window into an artificial hierarchy.

Create artificial hierarchy around any two connected and2 gates in the database.

Load a binary database (ZDB file), and create a graphics file for each module (SVG, PDF or POSTSCRIPT). This script works without a GUI and must be executed directly with starsh.

Usage:

Read a Spice netlist with X/Y annotations for each device and a side file that contains polygon definitions then this Plugin can be used to re-create a hierarchical database.

Add a main menu entry to load all hierarchical instances into the Cone window.

Userware example to highlight objects and annotate timing values.

Highlight and remove PODE and DUMMY devices by model/cell name patterns. Highlight devices py parameter name patterns.

Loop over the loaded database and highlight different devices (based on the model name) in a different color.

This example shows how to use the waveform parser to - read a DC analysis result file - traverse all curves defined in this file - highlight elements in the schematic from this data

This example shows how to use the waveform parser to - read a DC analysis result file - traverse all curves defined in this file - create value attributes for resistors and capacitors in the schematic

This example shows how to use the waveform parser to - read a DC analysis result file - traverse all curves defined in this file - highlight elements in the schematic from this data

This example shows how to use the waveform parser to - read a DC analysis result file - traverse all curves defined in this file - create voltage attributes on corresponding nets in the schematic

Read a side file that contains node names. Highlight all interconnected nodes in the same color.

Loop over the loaded database and highlight all pulldown devices and nets.

Loop over the loaded database and highlight reduced objects that are marked with the $CONSISTINGOF attribute (e.g. after $db oper mergeParallel).

Create a histogram of all W/L values in the database.

Open a binfile and loop over all cells in the database and remove the clock flag from all CGC cells.

Extend the popup menu with the options to ignore or grey out devices. The ignored devices are stored in the Mem window and can be undone.

Since the binlib file format becomes incompatible if the database structure changes here are two scripts that can be used to migrate the contents of a compiled binlib to a new binlib version.

Run the old version of *Vision to export the binlib to Tcl:

Run the new version of *Vision to import the Tcl and save a new version of the binlib:

Parse pcb netlist and create ZDB.

Supported formats: - siemens / mentor / xpedition - altium / protel - cadence / orcad

Open issues: - symbol / function creation - better/unified dict/list handling - unified data for one single zdb save code - power/ground nets - better pin directions - sections in orcad (?) - error handling - insts/primitives checks

Usage: *vision -userwareargs pcbimport.tcl \ "-altium {Altium Netlist.NET}" *vision -userwareargs pcbimport.tcl \ "-siemens {Xpedition Netlist.qcv}" *vision -userwareargs pcbimport.tcl \ "-cadence {OrCAD Netlist Part 1.dat} \ {OrCAD Netlist Part 2.dat} \ {OrCAD Netlist Part 3.dat}"

Insert a Userware menu to import Synplicity project files.

A Userware to visualize the results of the sta_report.tcl script.

This is a Userware to provide a widget to manage timing paths. The script sta_report.tcl executed in Altera’s TimeQuest tool will generate an output file that uses this PathVision Userware.

Insert a Userware menu to import Xilinx Vivado and Xilinx ISE project files.

Just create the userware menu

Create userware menu and immediately import project.xpr

Create userware menu, immediately import project.xpr and create project.set

Inspired by code from the XML Parser YAXMLP in wiki.tcl.tk/20146 from George Peter Staplin

Customize *Vision at startup by loading multiple scripts.

Extend the Popup menu of the Cone window and add the option to keep the selected and delete all other objects.

Add a new main menu entry to calculate the estimated chip area based on the Liberty area attribute.

Link the Parasitic view with a Layout viewer.

Parse a FastScan report file and display a pin list.

Parse and display a HyperFault report or log file.

Parse and display a HyperFault report or log file.

Extend the Popup menu with a function Load Members Into Memory that loads the members of the selected buses into the Mem window.

Basic transistor example.

Another transistor example.

Add main menu entries to load/append all highlighted objects/nets/instances into the main Cone window.

Merges parallel and serial transistors and resistors of parasitic networks.

Add a main menu entry to apply LUT/PLA symbols to LUT-style instances.

In order to be recognized as a LUT-style instance, there must be n inputs (2⇐n⇐10), exactly 1 output, and the instance must have an attribute INIT with an exact bit-width of 2^n.

Allow for deleting & creating hierarchies, rotating & moving transistor-level device instances, etc.

Extend the Popup menu with a Rename entry that allows for renaming of the selected object.

Warning: bad names (e.g. empty names, names of an existing objects, names containing hierarchy separators) may result in an invalid data base.

Mark all nets without parasitic info.

Replace all modules matching any of the given name patterns in the provided side file as a resistor device. Then merge all serial resistor devices.

Scan the database for top level R/C objects with a period (.) in a connected node name and move that object down the hierarchy to the path specified in the node name.

Parse a NanoTime report file and display all paths in a custom widget. Timing values are annotated in the schematic view. Individual paths can be displayed in the Cone window.

Usage:

After loading a NanoTime report, the tab 'NanoTime' shows the original report file, as well as the list of report items found in the file. Clicking a report item scrolls the report file to the corresponding position and highlights the path nodes of the report item.

The button 'Load Cone' loads the path nodes of the selected report item into StarVision’s/SpiceVision’s 'Cone window'. You can annotate the path with attribute values by checking some check boxes in the 'Show' section.

The button 'Load Mem' loads the path nodes into the 'Mem window'.

Checking 'Show Only Violating Items' updates the items list to only show report items which violate slack constraints; unchecking it will display all items.

Extend the Popup menu to traverse the design hierarchy.

Extend the popup menu with the option to load the next connected device in the Cone window.

Obfuscates all names of the loaded design and writes Verilog code to obfuscated directory structure. Generates obfuscated filesets and an corresponding map to reverse the obfuscation (e.g. in a NanoTime report).

This Userware example script establishes a socket connection between *Vision PRO (server) and an arbitrary Tcl-based application, e.g. tclsh (client). This file contains the code for both sides, the server and the client side.

Try it out: Source this file into a *Vision PRO tool AND into a standard "tclsh" and type commands at the tclsh prompt like

or

The first executes set db and $db flatattr $oid getMergedValue w in the *Vision process and sets the result to the val variable, the second executes the contents of the script variable.

Parse NDL files and create zdb. The proprietary netlist format is the gate-level design description language named 'Network Description Language' (NDL) used by LSI.

Parse a Pathmill report file and load the paths into the Cone window. On click, the values are displayed on the schematic.

Select Pathmill→Open Pathmill File (from main menu) and open the report file.

Parse tab-separated-value (TSV) file into zdb database.

where:

This is the C implementation of the readTSV.tcl userware. It is faster on processing large files but must be compiled be before usage.

Parse TSV (tab separated value) files and load the connectivity to zdb.

Parser for a tab-separated-value (TSV) file which looks like this:

where:

The C implementation tsv2zdb.c of this userware can be used to speed up the parsing process. The TCL implementation can be adjusted to the user’s requirements without recompiling.

Use the Cone Extraction API to find a path from a given start pin or node to primary input. If a cell contains only transistors then this cell is treated as a leaf cell, because the Cone Extraction cannot trace through transistors.

Extend the Popup menu to extract a path from a S, D or G pin of a transistor to power and ground. Go through resistors, inductors and D→S or S→D of NMOS or PMOS transistors.

Add more patterns to the gate recognition code.

Demonstrate the usage more highlight colors using permanent highlight.

Search for hierarchical pins and extract the driver. The menu entry "Search Pins/Search" opens a dialog to search for hierarchical pins. Results are displayed in the "Mem" window. The "Mem" window’s popup menu entry "Search Pins/Extract to Driver" searches for the driver of the selected pin and appends the result to the "Cone" window.

Parse a PrimeTime report file and display all paths in a dialog window. Timing values are annotated in the schematic view. Individual paths can be displayed in the Cone window.

Features:

Print each module of the loaded design as a PDF file.

Create a progress bar for a long running function.

General purpose script to prune any kind of loaded netlist data.

RTLvision PRO userware to implement a GUI showing the use of server.tcl and client.tcl.

Start Quartus in the background, start a server inside Quartus and connect to this server (RTLvision is the client). Now a Quartus project can be created, the timing netlist can be transferred and the timing paths can be queried from Quartus and visualized in RTLvision.