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612 | ###############################################################################
# Copyright (c) 2011-2024 by Altair Engineering, Inc.
# All rights reserved.
#
# Altair Engineering, Inc. makes this software available as part of the Vision
# tool platform. As long as you are a licensee of the Vision tool platform
# you may make copies of the software and modify it to be used within the
# Vision tool platform, but you must include all of this notice on any copy.
# Redistribution without written permission to any third party, with or
# without modification, is not permitted.
# Altair Engineering, Inc. does not warrant that this software is error free
# or fit for any purpose. Altair Engineering, Inc. disclaims any liability for
# all claims, expenses, losses, damages and costs any user may incur as a
# result of using, copying or modifying the software.
# =============================================================================
# @userware
# Export Quartus DB as TCL
# @section
# Link to Other Tools
# @description
# This script contains procedures to query netlist information from the
# Quartus database and writes out `$db load ...` statements.
# @files
# quartus/accessDB.tcl
# @tag
# rtl verilog fpga
###############################################################################
##
# Load utility procedures.
#
source [file join [file dirname [info script]] qutils.tcl]
# -----------------------------------------------------------------------------
# _createCells - Iterates through every cell and create the primitive
# definitions in zdb.
# -----------------------------------------------------------------------------
#
proc AccessDB:_createCells {fileid guessBuses} {
global CellHash
##
# Get a collection of all cells and count the number of elements.
#
set cells [get_cells * -hierarchical]
set count [get_collection_size $cells]
##
# Loop over each cell in the collection.
#
set n 0
foreach_in_collection cell $cells {
##
# Add progress update calls.
#
if {[expr {[incr n] % 200}] == 0} {
puts $fileid "if \{\[zprogress update \"\" $n $count\]\} return"
}
##
# Get the name of this cell.
#
set cellName [get_cell_info -wysiwyg_type $cell]
##
# Here we assume that cells ending with _io are top level I/O ports.
#
if {[string match "*_io" $cellName]} {
continue
}
##
# Loop over all ports of this cell and create a list of ports and
# their corresponding direction.
#
set portList {}
foreach_in_collection pin [get_cell_info $cell -pins] {
##
# Get the port name.
#
set portName [get_pin_info -suffix $pin]
##
# Get the direction of the port.
#
set dir "inout"
if {[get_pin_info -is_in_pin $pin]} {set dir "input"}
if {[get_pin_info -is_out_pin $pin]} {set dir "output"}
##
# If the pin has a known name then do the corresponding action.
#
switch -exact $portName {
"clk" {append dir ".clk"}
"cin" -
"sload" -
"sclr" -
"sharein" -
"aclr" {append dir ".top"}
"cout" -
"aload" -
"shareout" {append dir ".bottom"}
}
##
# Add the direction and the name to the list of ports.
#
lappend portList [list $portName $dir]
}
if {[info exists CellHash($cellName:$portList)]} {
set CellHash(cell2name:$cell) $CellHash($cellName:$portList)
continue
}
if {![info exists CellHash(count:$cellName)]} {
set CellHash(count:$cellName) 0
}
set origCellName $cellName
incr CellHash(count:$cellName)
##
# Currently each instance has its own cell. Make the cell name unique
# by appending the cell id to the name.
#
append cellName _$CellHash(count:$cellName)
set CellHash($origCellName:$portList) $cellName
set CellHash(cell2name:$cell) $cellName
##
# Specify the primitive function.
#
set function "unknown"
if {[string match "*io_?buf" $origCellName]} {
set function "BUF"
##
# Sort portList: first output, then input and then inout ports.
#
set portList [lsort -command AccessDB:_sortByDir $portList]
}
##
# Call Zdb:_createCell
#
Zdb:_createCell $fileid $guessBuses $cellName $function $portList
}
}
# -----------------------------------------------------------------------------
# _createCell - Create a cell with the given info in zdb.
# -----------------------------------------------------------------------------
#
proc Zdb:_createCell {fileid guessBuses cellName function portList} {
##
# Sort the port list by the port name. This is only needed if guessBuses
# is enabled.
#
if {($function == "unknown") && $guessBuses} {
set portList [lsort -index 0 -dictionary $portList]
}
##
# Loop over all ports of this cell to generate a GEN symbol shape.
#
set sym ""
if {$function == "unknown"} {
set sym "-attr \{@symbol=GEN"
foreach pi $portList {
append sym " port [lindex $pi 0] [lindex $pi 1]"
}
append sym "\}"
}
##
# Write out the statement to load a primitive cell.
#
QuUtils:WriteLine $fileid "\$db load primitive $cellName $function $sym"
##
# Loop over all ports of this cell.
#
foreach portInfo $portList {
set portName [lindex $portInfo 0]
set dir [lindex $portInfo 1]
set flag ""
switch -glob -- $dir {
"*.top" {set dir [string range $dir 0 end-4]}
"*.bottom" {set dir [string range $dir 0 end-7]}
"*.clk" {
set flag "-flag clock"
set dir [string range $dir 0 end-4]
}
default {}
}
##
# Write out a statement to load a port to the cell.
#
QuUtils:WriteLine $fileid " \$db load port $portName $dir $flag"
}
##
# If guessBuses is enabled then write out code to guess port buses for
# the interface of the just created cell.
#
if {$guessBuses} {
puts $fileid "set cell \[\$db search primitive $cellName\]; \
if \{!\[\$db oid isnull \$cell\]\} \{ \
\$db oper guessPortBus \$cell \\\[ \\\] \
\}"
}
}
# -----------------------------------------------------------------------------
# _sortByDir - Sort portInfo list by port direction.
# -----------------------------------------------------------------------------
#
proc AccessDB:_sortByDir {a b} {
if {[string match "output*" [lindex $a 1]]} {
return -1
} else {
return 1
}
return 0
}
# -----------------------------------------------------------------------------
# _createTop - Create the top level module and its interface.
# -----------------------------------------------------------------------------
#
proc AccessDB:_createTop {fileid topName guessBuses} {
##
# Get a collection of all ports and count the number of elements.
#
set ports [get_ports *]
set count [get_collection_size $ports]
##
# Load the top level module.
#
QuUtils:WriteLine $fileid "# Top level module"
QuUtils:WriteLine $fileid "\$db load module $topName -top"
##
# Loop over each port in the collection.
#
set portList {}
set n 0
foreach_in_collection port $ports {
##
# Add progress update calls.
#
if {[expr {[incr n] % 200}] == 0} {
puts $fileid "if \{\[zprogress update \"\" $n $count\]\} return"
}
##
# Get the direction of the port.
#
set dir "unknown"
if {[get_port_info -is_output_port $port]} {
set dir "output"
}
if {[get_port_info -is_input_port $port]} {
set dir "input"
}
if {[get_port_info -is_inout_port $port]} {
set dir "inout"
}
##
# Get the name of the port.
#
set portName [get_port_info -name $port]
##
# Append the name and the direction to the list of ports.
#
lappend portList [list $portName $dir]
}
##
# Sort the port list by the port name. This is only needed if guessBuses
# is enabled.
#
if {$guessBuses} {
set portList [lsort -index 0 -dictionary $portList]
}
##
# Loop over each port/direction pair in the port list.
#
foreach portInfo $portList {
set portName [lindex $portInfo 0]
set dir [lindex $portInfo 1]
##
# Write out a statement to load a port to the cell.
#
QuUtils:WriteLine $fileid " \$db load port $portName $dir"
}
##
# Write code to the output file to get the OID of the top module.
#
puts $fileid "set top \[\$db search module $topName\]; \
if \{\[\$db oid isnull \$top\]\} \{ \
puts stderr \"Cannot find top module $topName\"; \
exit 1 \
\}"
##
# If guessBuses is enabled then write out code to guess port buses for
# the top level module interface.
#
if {$guessBuses} {
puts $fileid "\$db oper guessPortBus \$top \\\[ \\\]"
}
}
# -----------------------------------------------------------------------------
# _createInst - Write out "$db load inst" commands for all instances.
# -----------------------------------------------------------------------------
#
proc AccessDB:_createInst {fileid} {
global CellHash
##
# Get a collection of all cells and count the number of elements.
#
set cells [get_cells * -hierarchical]
set count [get_collection_size $cells]
##
# Loop over each cell in the collection.
#
foreach_in_collection cell $cells {
##
# Add progress update calls.
#
if {[expr {[incr n] % 200}] == 0} {
puts $fileid "if \{\[zprogress update \"\" $n $count\]\} return"
}
##
# Get the name of this cell.
#
set cellName [get_cell_info -wysiwyg_type $cell]
##
# Here we assume that cells ending with _io are top level I/O ports.
#
if {[string match "*_io" $cellName]} {
continue
}
##
# Get the name of the cell for this instance.
#
set cellName $CellHash(cell2name:$cell)
##
# Get the name of this instance.
#
set instName [get_cell_info -name $cell]
##
# check if this instance is a register.
#
set attr ""
set reg [get_registers -nowarn $instName]
if {[get_collection_size $reg] == 1} {
append attr " -attr IS_REGISTER=1"
if {[get_register_info -is_latch $reg]} {
append attr " -attr IS_LATCH=1"
}
}
if {[get_collection_size $reg] > 1} {
##
# Need to figure out what's going on here.
#
}
##
# Write out the "$db load inst" command.
#
QuUtils:WriteLine $fileid "\$db load inst $instName ${cellName}$attr"
}
}
# -----------------------------------------------------------------------------
# _createConnectivity - Assuming all cells have been defined and instantiated,
# this procedure will iterate again through all cells
# and extract connectivity information.
# The "$db load net" command is used to connect output
# pins with all input pins that they drive.
# -----------------------------------------------------------------------------
#
proc AccessDB:_createConnectivity {fileid guessBuses} {
##
# Get a collection of all nets and count the number of elements.
#
set nets [get_nets]
set count [get_collection_size $nets]
set n 0
##
# Create an array with all clocks in the design.
#
array set _clockHash {}
foreach_in_collection clk [all_clocks] {
set _clockHash([get_clock_info -name $clk]) 1
}
foreach_in_collection net $nets {
##
# Add progress update calls.
#
if {[expr {[incr n] % 200}] == 0} {
puts $fileid "if \{\[zprogress update \"\" $n $count\]\} return"
}
##
# Get the net name.
#
set netName [get_net_info -name $net]
##
# Get the cell name.
#
set pin [get_net_info -pin $net]
set cell [get_pin_info -parent_cell $pin]
set cellName [get_cell_info -wysiwyg_type $cell]
##
# Get the instance name of this cell.
#
set instName [get_cell_info -name $cell]
##
# Create the line to load the net and all its connections.
#
set line "\$db load net $netName "
##
# If this is an I/O cell then connect the net to a port.
#
set type [get_node_info -type $pin]
if {$type == "port" || [string match "*_io" $cellName]} {
append line " -port $instName"
} else {
set pinName [get_pin_info -suffix $pin]
append line " -pin $instName $pinName"
}
##
# Loop over all fanout edges.
#
foreach edge [get_node_info $pin -fanout_edges] {
##
# Get destination ipin.
#
set ipin [get_edge_info $edge -dst]
if {[get_node_info -type $ipin] == "port"} {
##
# Get the pin name.
#
set pinName [get_port_info -name $ipin]
append line " -port $pinName"
continue
}
##
# Get the pin name.
#
set pinName [get_pin_info -suffix $ipin]
##
# Get the parent cell of this ipin.
#
set parentCell [get_pin_info $ipin -parent_cell]
##
# Get the name of the parent cell.
#
set parentCellName [get_cell_info -wysiwyg_type $parentCell]
##
# Get the instance name of the parent cell.
#
set parentInstName [get_cell_info -name $parentCell]
##
# If this is an I/O cell then connect the net to a port.
#
if {[string match "*_io" $parentCellName]} {
append line " -port $parentInstName"
} else {
append line " -pin $parentInstName $pinName"
}
}
##
# If this is a clock net then add an attribute to the net.
#
if {[info exists _clockHash($netName)]} {append line " -attr CLOCK=1"}
##
# Write out the 'load net' line.
#
QuUtils:WriteLine $fileid $line
}
##
# If guessBuses is enabled then write out code to guess net buses.
#
if {$guessBuses} {
puts $fileid "\$db oper guessNetBus \$top \\\[ \\\]"
}
}
# =============================================================================
# Copy2zdb - Transfer the netlist from Quartus to RTLvision.
# =============================================================================
#
proc AccessDB:Copy2zdb {fileid {guessBuses 0} {hierSep ""}} {
global CellHash
array unset CellHash
##
# Write a header to the generated script.
#
QuUtils:WriteLine $fileid \
"# Database access by accessDB.tcl"
##
# Dump the command to open a new zdb.
#
puts $fileid "set db \[zdb new\]"
##
# Get the name of the top level entity.
#
set topName [get_name_info -info entity_name [get_top_level_entity]]
##
# Create all cell definitions.
#
puts $fileid "zprogress push \"Create Cells\" 0.15"
AccessDB:_createCells $fileid $guessBuses
puts $fileid "if \{\[zprogress pop\]\} \{return\}"
##
# Create the top level module.
#
puts $fileid "zprogress push \"Create Top Module\" 0.2"
AccessDB:_createTop $fileid $topName $guessBuses
puts $fileid "if \{\[zprogress pop\]\} \{return\}"
##
# Fill the top module: add all instances.
#
puts $fileid "zprogress push \"Create Instances\" 0.5"
AccessDB:_createInst $fileid
puts $fileid "if \{\[zprogress pop\]\} \{return\}"
##
# Fill the top module: create connectivity.
#
puts $fileid "zprogress push \"Create Connectivity\" 1.0"
AccessDB:_createConnectivity $fileid $guessBuses
puts $fileid "if \{\[zprogress pop\]\} \{return\}"
##
# If guessBuses is enabled then write out code to guess inst arrays.
#
if {$guessBuses} {
puts $fileid "\$db oper guessInstArray \$top \\\[ \\\]"
}
##
# Write code to the output file to validate the created zdb.
#
puts $fileid "if \{\[catch \{\$db validate\} msg\]\} \{ \
puts stderr \$msg; \
exit 1 \
\}"
##
# Write code to the output file to re-create the hierarchy
# based on the given hierarchy separator.
#
if {$hierSep != ""} {
puts $fileid "\$db oper createHier \$top $hierSep"
}
##
# Return the name of the created top module.
#
return $topName
}
|