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319 | ###############################################################################
# Copyright (c) 2014-2024 by Altair Engineering, Inc.
# All rights reserved.
#
# Altair Engineering, Inc. makes this software available as part of the Vision
# tool platform. As long as you are a licensee of the Vision tool platform
# you may make copies of the software and modify it to be used within the
# Vision tool platform, but you must include all of this notice on any copy.
# Redistribution without written permission to any third party, with or
# without modification, is not permitted.
# Altair Engineering, Inc. does not warrant that this software is error free
# or fit for any purpose. Altair Engineering, Inc. disclaims any liability for
# all claims, expenses, losses, damages and costs any user may incur as a
# result of using, copying or modifying the software.
# =============================================================================
# @userware
# Dump Design Metrics as JSON
# @section
# Create Reports
# @description
# Analyze a given ZDB and produce the following design metrics for each
# design (top level module):
#
# * Module name
# * Number of ports
# * Number of input ports
# * Number of output ports
# * Number of bi-dir ports
# * Number of instances in the module
# * Number of nets in the module
# * Number of registers
# * Number and types of sub-module instances (including standard
# cells) instantiated.
# * Length of scan-chains
# * Number of clock domains
#
# @files
# cust25/designMetrics.tcl
# @tag
# report zdb
###############################################################################
package require json::write
# -----------------------------------------------------------------------------
# _analyzePorts - Process all ports and portBuses in the given module.
# -----------------------------------------------------------------------------
#
proc DesignMetrics:_analyzePorts {out db module} {
global DesignMetrics
##
# Initialize a hash table for storing the port statistic.
#
foreach dir {"input" "output" "inout" "unknown"} {
set DesignMetrics($module:ports:$dir) 0
}
##
# Loop over all ports and collect ports of the same direction.
#
$db foreach portBus $module portBus {
incr DesignMetrics($module:ports:[$db directionOf $portBus])
}
$db foreach port $module port {
if {[$db isBusMember $port]} {
continue
}
incr DesignMetrics($module:ports:[$db directionOf $port])
}
}
# -----------------------------------------------------------------------------
# _analyzeInsts - Process all instances in the given module.
# -----------------------------------------------------------------------------
#
proc DesignMetrics:_analyzeInsts {out db module} {
global DesignMetrics
##
# Initialize instance specific variables.
#
set DesignMetrics($module:instCount) 0
set DesignMetrics($module:registerCount) 0
set DesignMetrics($module:primInstCount) 0
set DesignMetrics($module:subModNames) {}
set DesignMetrics($module:subPrimNames) {}
##
# Loop over all instances in this module.
#
$db foreach inst $module inst {
##
# Count the total number of instances.
#
incr DesignMetrics($module:instCount)
##
# If the current instance is flagged as a clocked cell then
# count it as a register.
#
if {[$db flag [$db down $inst] is clock]} {
incr DesignMetrics($module:registerCount)
continue
}
##
# Collect metrics for instantiated primitive or sub-modules.
#
if {[$db isModule $inst]} {set key "subMod"} else {set key "subPrim"}
set cname [$db oid cname $inst]
if {![info exists DesignMetrics($module:$key:$cname)]} {
lappend DesignMetrics($module:${key}Names) $cname
set DesignMetrics($module:$key:$cname) 0
}
incr DesignMetrics($module:$key:$cname)
}
}
# -----------------------------------------------------------------------------
# _analyzeNets - Process all nets and netBuses in the given module.
# -----------------------------------------------------------------------------
#
proc DesignMetrics:_analyzeNets {out db module} {
global DesignMetrics
##
# Initialize net specific variables.
#
set DesignMetrics($module:nets) 0
set DesignMetrics($module:netBuses) 0
##
# Count the number of nets and netBuses.
#
$db foreach netBus $module netBus {incr DesignMetrics($module:nets)}
$db foreach net $module net {incr DesignMetrics($module:netBuses)}
}
# -----------------------------------------------------------------------------
# _writeJson - Write out the collected data as JSON format.
# -----------------------------------------------------------------------------
#
proc DesignMetrics:_writeJson {db out} {
global DesignMetrics
set allMetrics {}
$db foreach module module {
##
# Get the name of this module.
#
set modName [$db attr $module getValue "RTL_Name"]
if {$modName == ""} {set modName [$db oid oname $module]}
##
# Create module metrics.
#
set moduleMetrics {}
lappend moduleMetrics "name" [json::write string $modName]
##
# Create port metrics.
#
set portsMetrics {}
set totalNoPorts 0
foreach dir {"input" "output" "inout" "unknown"} {
set value $DesignMetrics($module:ports:$dir)
if {$value == 0} {
continue
}
incr totalNoPorts $value
lappend portsMetrics $dir $value
}
lappend portsMetrics "total" $totalNoPorts
lappend moduleMetrics "ports" [json::write object {*}$portsMetrics]
##
# Create net metrics.
#
set netsMetrics {}
if {$DesignMetrics($module:nets) > 0} {
lappend netsMetrics "num" $DesignMetrics($module:nets)
}
if {$DesignMetrics($module:netBuses) > 0} {
lappend netsMetrics "numBuses" $DesignMetrics($module:netBuses)
}
lappend moduleMetrics "nets" [json::write object {*}$netsMetrics]
##
# Create inst metrics.
#
set instsMetrics {}
lappend instsMetrics "registers" $DesignMetrics($module:registerCount)
lappend instsMetrics "total" $DesignMetrics($module:instCount)
##
# Create sub module metrics.
#
set subModules {}
lappend subModules "num" [llength $DesignMetrics($module:subModNames)]
set subDetails {}
foreach cname $DesignMetrics($module:subModNames) {
set subInfo {}
lappend subInfo "num" $DesignMetrics($module:subMod:$cname)
##
# Process module attributes.
#
set paramMetrics {}
set cell [$db search cell $cname]
$db attr $cell foreach attr {
##
# Skip internal attributes.
#
if {[string match "RTL_Name=*" $attr]} {
continue
}
if {[string match "@*" $attr]} {
continue
}
if {[string match "#*" $attr]} {
continue
}
if {[string match "\$*" $attr]} {
continue
}
set equalPos [string first "=" $attr]
set attrName [string range $attr 0 $equalPos-1]
set attrValue [string range $attr $equalPos+1 end]
##
# Try to convert this attribute value into a decimal value.
#
if {[catch {
set attrValue [zdb formatvalue fromverilog $attrValue]
} errMsg]} {
zmessage print ERR \
"Attribute $attrName of cell $cname: $errMsg"
continue
}
lappend paramMetrics $attrName [format "%lu" $attrValue]
}
lappend subInfo "params" [json::write object {*}$paramMetrics]
lappend subDetails $cname [json::write object {*}$subInfo]
}
lappend subModules "details" [json::write object {*}$subDetails]
lappend instsMetrics "sub_modules" [json::write object {*}$subModules]
lappend moduleMetrics "instances" [json::write object {*}$instsMetrics]
lappend allMetrics "module" [json::write object {*}$moduleMetrics]
}
##
# Write out the module metrics as a JSON object (each module in a
# separate line)
#
::json::write indented true
::json::write aligned true
puts $out [json::write object {*}$allMetrics]
::json::write indented false
::json::write aligned false
}
# =============================================================================
# StartAnalyze - Start analyzing the given database.
# =============================================================================
#
proc DesignMetrics:StartAnalyze {out db} {
global DesignMetrics
##
# Initialize the result table.
#
array unset DesignMetrics
array set DesignMetrics {}
##
# Loop over each module and analyze each module.
#
$db foreach module module {
DesignMetrics:_analyzePorts $out $db $module
DesignMetrics:_analyzeInsts $out $db $module
DesignMetrics:_analyzeNets $out $db $module
}
##
# Write out the result as JSON format.
#
DesignMetrics:_writeJson $db $out
}
##
# Check args.
#
if {$argc != 2} {
error "Wrong args.\nUsage $argv0 <ZDB-BINFILE> <OUTFILE>"
}
set binfile [lindex $argv 0]
set outfile [lindex $argv 1]
set db [zdb open $binfile]
set out [open $outfile "w"]
DesignMetrics:StartAnalyze $out $db
$db close
close $out
exit
|