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114 | ###############################################################################
# Copyright (c) 2006-2024 by Altair Engineering, Inc.
# All rights reserved.
#
# Altair Engineering, Inc. makes this software available as part of the Vision
# tool platform. As long as you are a licensee of the Vision tool platform
# you may make copies of the software and modify it to be used within the
# Vision tool platform, but you must include all of this notice on any copy.
# Redistribution without written permission to any third party, with or
# without modification, is not permitted.
# Altair Engineering, Inc. does not warrant that this software is error free
# or fit for any purpose. Altair Engineering, Inc. disclaims any liability for
# all claims, expenses, losses, damages and costs any user may incur as a
# result of using, copying or modifying the software.
# =============================================================================
# @plugin
# Check for Multiple Drivers
# @namespace
# MultiDriverCheck
# @section
# Analyze the Loaded Database
# @description
# Loop over all signals and check if a signal has more than one driver.
# @non-interactive
# @files
# multiDriverCheck.tcl
# @example
# demo/verilog/bus85.f
# @cmdline
# -F @example[0]
# -userware @files[0]
# @tag
# rtl verilog zdb netlist
###############################################################################
# =============================================================================
# Init - Initialize the plugin.
# =============================================================================
#
proc MultiDriverCheck:Init {} {
gui database runOrRegisterChangedCallback MultiDriverCheck:Run
}
# =============================================================================
# Finit - Finalize the plugin.
# =============================================================================
#
proc MultiDriverCheck:Finit {} {
gui database removeChangedCallback MultiDriverCheck:Run
}
# =============================================================================
# Run - Loop over all signals and check if a signal has more than
# one driver.
# =============================================================================
#
proc MultiDriverCheck:Run {db} {
##
# Return if the database is empty.
#
if {$db == {}} {
return
}
set resList {} ;# result List
set top [$db get_top_design]
$db flat foreach signal $top sig {
##
# skip power, ground and negpower nets
#
if {[$db isPgNet $sig]} {
continue
}
set driverCount 0
$db flat foreach pin $sig pin {
if {[$db oid type $pin] == "port"} {
continue
}
set dir [$db directionOf $pin]
if {$dir == "output" || $dir == "inout"} {
incr driverCount
if {$driverCount == 2} {
lappend resList $sig
break
}
}
}
}
##
# Clear and activate the Mem Window
#
gui mem clear
gui window show Schem
gui window show Mem
##
# Store the result into the Mem Window.
#
gui mem append $resList
}
# =============================================================================
# Call the initialization procedure.
# =============================================================================
#
MultiDriverCheck:Init
|