Solder Mark Violation

Verify the solder mask is in the PCB design and if it overlaps with routing patterns.

In design, moving components and leaving the solder mask on the design may result in critical errors. To eliminate human error, it is necessary to analyze the solder mask.

The Solder Mark Violation dialog contains the following sections:
  • Solder Mask Layer Definition: Select the solder mask location for the top and bottom layer.
  • Option
    • Ignore Solder Mask under Specific Component: Skip the analysis for solder masks under specified components.
  • Checking:
    • Routed Patterns overlapped with Solder Mask Area: Verify there is pattern overlapping in the solder mask area.
    • Routed Patterns of Multiple Nets under Same Solder Mask Area: Verify there is overlapping with two or more net patterns in the solder mask area.
    • Board Figure Solder Mask Clearance: Verify there is pattern overlapping in the board figure solder mask area.