# Ground Coverage

This item checks for via locations and via area coverage.

Ground surface has influence on the ground signal’s stability. Therefore, in order to reduce EMI problems, ground surface handling should be done more carefully. Well-designed ground surface structures are very effective for EMI protection. In some bad designs, they become a critical element of EMI problems.

Improper ground structure causes ground fluctuation, signal distortion and EMI problems. If ground planes are located at all layers, they should be connected with proper spacing between VIAs.

Many current paths through abundant vias in order to make shorter current return paths but their locations are very important.

In many high-speed design practices, all signal nets are routed first then the ground structure is constructed by automatically filling copper in empty areas. Then vias are placed to connect those copper areas on different layers.

Checking for via locations and their area coverage helps to improve the ground stability.
• Item: Enter item name.
• Net: Select a copper net group.
• Options:
• Coverage base type: Select a copper area calculation type.
• Layer: PollEx DFE calculates all copper regions for layers on which nets in the net group that was selected in ② are routed.
• Single Copper: PollEx DFE calculates copper regions of the nets in the net group that was selected in ②.
• Minimum Ratio (%): Assign a ratio of calculated via coverage area compared to the entire copper area.

## Return Current

Solutions to the return signal current plane jumping problem are:
• Restrict each trace to remain on the layer it starts.
• Restrict traces to remain on either side of the ground plane they start out nearest.
• Provide ground vias next to every signal via explicitly for the purpose return current jump between layers.
• Make sure there are plenty of ground vias everywhere. Regardless of where the signal via occurs, its return current will not have to divert far to find a place to jump.

## Capacitance of Vias

${C}_{via}\text{\hspace{0.17em}}=\text{\hspace{0.17em}}\frac{1.41{\epsilon }_{r}T{D}_{1}}{{D}_{2}\text{\hspace{0.17em}}-\text{\hspace{0.17em}}{D}_{1}}$
Where,
${D}_{2}$
Diameter of hole in ground planes, in.
${D}_{1}$
$T$
Thickness of PCB or dielectric, in.
${\epsilon }_{r}$
Relative dielectric constant of PCB material.
$C$
Parasitic via capacitance, pF.

## Inductance of Vias

${L}_{via\text{\hspace{0.17em}}}\text{\hspace{0.17em}}=\text{\hspace{0.17em}}5.08h\left[\mathrm{ln}\text{\hspace{0.17em}}\left(\frac{4h}{d}\right)\text{\hspace{0.17em}}+\text{\hspace{0.17em}}1\right]$
Where,
$h$
Length of via, in.
$d$
Diameter of via, in.
$L$
Inductance of via, nH.