Linear Regulator

This item tracks the voltage and signal lines in the circuit, calculates the voltage value of each net, and checks whether the all linear regulator connected to the net is within the allowable voltage range.



Figure 1.
  • Component: Select Linear Regulator component group to be checked.
  • V_Input Pin: Assign power input pin information of regulator. You can assign pin number using Pin Number or Pin Property which contain pin number information.


    Figure 2.
  • Power Net: Select power net group to which Linear Regulator components are connected.
  • Ground Net: Select ground net group to which Linear Regulator components are connected.
  • Allowed V_In_Min: Set the allowable minimum power input voltage of this component. You can set this by entering the allowable value directly or select the property name which contain allowable value.


    Figure 3.
  • Allowed V_In_Max: Set the allowable maximum power input voltage of this component. You can set this by entering the allowable value directly or select the property name which contain allowable value.


    Figure 4.
  • Absolute Maximum[V]: Set the allowable absolute maximum power input voltage of this component. You can set this by entering the allowable value directly or select the property name which contain allowable value. You can also assign tolerance of this test.


    Figure 5.

Stress Test Option

Set whether passive components are considered short or open when navigating signals and power lines.

  1. Double-click the empty field to open the Stress Test Option dialog.


    Figure 6.
  2. Power Net Composite Section: In this step, we declare the component to be processed short and the component to be opened during power trace navigation. Since Stress Test is a DC level test, the capacitor is considered as open and inductor is considered as short. And normally the resistor is considered as open, because the current of power net is so big that the IR-Drop can’t be ignored. Since TR and FET are used as switching components, they are regarded as short when voltage navigating.
    1. Open Component: Select the component group to be regarded as short when power trace navigating.
    2. Short Component: Select the component group to be regarded as short when power trace navigating.


      Figure 7.
  3. Signal Net Composite Section: In this section, we declare the component to be processed short and the component to be opened during signal trace navigation. Since Stress Test is a DC level test, the capacitor is considered as open and inductor is considered as short. And normally the resistor is considered as short, because the current of signal net is so small that the IR-Drop can be ignored.
    1. Open Component: Select the component group to be regarded as short when signal trace navigating.
    2. Short Component: Select the component group to be regarded as short when signal trace navigating.


    Figure 8.
  4. Short Pin Section: TR or FET is a device with three pins, so it needs information about pins connected to each other during short processing.
    1. By Pin Name: Declare pin paring information as pin name. If there is more than one condition, the separator “,” is used.
    2. By Signal Name: Declare pin paring information as signal name. If there is more than one condition, the separator “,” is used.


      Figure 9.
  5. Exclude Component: Select component group to be excluded during test.


    Figure 10.