Data Line Analysis

Analyze interconnect network of data byte group nets of DDR BUS in time domain to obtain the eye diagrams and transient waveforms which are different views of the signal delay and distortion.

When performing an Automatic DDR Bus Simulation, please consider the following :

  1. Net Topology Review: Please review of the net topology for Data, Address, Command, and Control nets in advance.
  2. Power Setting: Please set power as 0V.
  3. Floating Nets: Please verify that there are no floating nets.

Creating a network analysis model starts with selecting data strobe net and data byte net from the net listing. The net name is initially assigned to the model name which can be changed by users. To analysis read and write cycle, CPU component must be selected for write cycle analysis and MEMORY component must be selected for read cycle analysis using Active Driver Pin.

Click Import to select required DDR operation speed then all required timing parameters are automatically filled with pre-defined value in JEDEC specification.
Figure 1.


Clicking Device Models allows you to view the device models selected for the output and input pins. Users can change the device model selection when multiple models are available for the pin.
Figure 2.


The analysis is performed upon selecting Run Analysis menu.

Eye Diagram analysis is running transient circuit simulation on the network model to obtain eye diagrams at the input nodes. An eye diagram or eye pattern is obtained from overlapping multiple waveforms at the receiver node of a net generated by randomly selected high/low states of the input signals for the selected net and adjacent nets. The coupling effects from the adjacent nets are reflected in the waveforms. Prior to running analysis, you can change the analysis control parameters such as the number of random pulses and bit pattern style.

Upon completion of the analysis, the eye diagrams at input nodes are displayed in the waveform viewer. You can also view the required eye-mask and setup/hold margin of each output pin. The eye diagram waveform data can be saved in a file with the use of Save menu. Save menu saves the file in Signal_Integrity/Waveform directory under the PCB project folder. The model name plus .spe is used for the file name. The saved eye diagram waveform data can be read into the waveform viewer alone or together with other eye diagram waveform data.
Figure 3.


Figure 4.


The analysis results can be listed in a table form by clicking Show Report tab. They can be also shown in MS Excel.

The Analysis > Signal Integrity > Data Line Analysis menu enables you to analyze data byte group nets in a one operation step.

There are three Node Selection Modes:
  1. Individual nodes - This mode is used when a user wants to view one waveform each for address or data lines, excluding the clock signal (Reference). For example, the following are the example of viewing each of the five A0 lines separately.
    Figure 5.


    Figure 6.


    Figure 7.


    Figure 8.


    Figure 9.


  2. Single input node - This mode is used when a user wants to view only the plus and minus pairs of the clock signal and it displays two waveforms. Input nodes include IC13_K7(i), IC14_K7(i), IC15_K7(i), IC16_K7(i) and IC13_K8(i), IC14_K8(i), IC15_K8(i), and IC16_K8(i) that are DDR memory side. For instance, clicking on IC14_K7(i) of the Clock automatically selects IC14_K8(i) as below. They are a pair.
    Figure 10.


  3. All input nodes in a component - This mode displays both the address and the plus/minus pairs of the clock signal simultaneously showing three waveforms. For example, clicking on IC13_P3(i) of the Address automatically selects IC13_K7(i) and IC13_K8(i) of the clock. Selecting IC13_K7(i) of the Clock will also automatically choose IC13_P3(i) of the Address and IC13_K8(i) of the clock.
    Figure 11.