Altair PollEx 2025 Release Notes

Highlights

PollEx Modeler
PCB
  • Added a feature to search for Vias in the PCB Explorer.
PollEx Verification
Technical Cleanliness
  • Enhanced the Exposed Copper calculation algorithm for the more accurate Hazard area analysis.
  • Enhanced the calculation algorithm performance to reduce the time to analyze the Hazard area.
DFE
  • Added User Defined Excel Format For Statistic menu to Excel report type allowing to manage accumulated Test Count and Fail Count for each Item.
DFE+
  • Enhanced the IR Drop item to check a Composite Power Net, enabling analysis of the IR drop across the entire power structure, including passive components.

New Features

PollEx Verification
  • Added a feature highlighting failure and warning items in the Summary Sheet on the DFM Excel Report.

Enhancements

PollEx Modeler
PCB
  • Enhanced the Ultra Librarian part search feature in Properties - Parts to utilize the Ultra Librarian part names.
Logic
  • Renamed the following menu naming to align with the PCB: Option to Verification, Redmark to Collaboration.
ECAD Interface
  • Enhanced Siemens PADS importer to include Net Class property data.
  • Enhanced Cadence Allegro importer to define multiple Board Outline layers.
  • Enhanced Altium Designer importer to recognize the KEEPOUT objects not the RECORD type’s BOARD.
  • Enhanced Allegro Fabmaster importer to recognize the copper polygon shapes.
  • Added an option to define the Zero Suppression settings in the Gerber (RS-274D/274X) import dialog in PCB and CAM.
  • Enhanced Gerber (RS-274D/274X) importer to support the Excellon Drill format.
  • Enhanced Gerber (RS-274D/274X) importer to recognize the Thermal Relief shapes.
  • Enhanced Ansys SIwave exporter to apply pre-defined layer colors.
  • Enhanced text scale for the Altium Designer Schematic importer of Logic.
PollEx Verification
DFM
  • Added a feature to import and export the String Item list from the file(*.txt) in the String Filter Set Up dialog.
  • Added an option to check Conveyed Edge Gaps of the Board Outline in the Board Spacing Item.
  • Added an option in the Connected Pattern Direction item to define the Pattern Measure Base.
  • Added an option in the Connected Pattern Direction item to exclude patterns in the Copper plane or Teardrop area.
  • Added an option to check the Patterns connected with Pad’s short side in the Connected Pattern Direction item.
  • Added an option in the Conformal Coating item to check the clearance between the coated/non-coated area and holes.
  • Added an option in the Conformal Coating item to check the clearance between the coated area and the non-coated component.
  • Added an option in the Teardrop item to define target Vias by Hole Size and Annular Ring Size.
  • Added an option in the Teardrop item to set the Pad Measure Base for the Minimum length of Teardrop check.
  • Added a Component Measure Base option (COC+Pad/Solder Mask Overlapped) in the Screw2 item.
  • Added a Component Measure Base option (COC+Pad/Solder Mask Overlapped) in the Reverse Placement Spacing item.
  • Enhanced algorithm to distinguish between SMD and NSMD Pad types in the Solder Resist Pad item.
  • Added an option in the Solder Resist Pad item to combine the overlapped solder mask objects.
  • Added an option in the Fiducial Mark item to check the Pad and Solder Mask Annular Ring size of the Fiducial Mark.
  • Added an option in the Fiducial Mark item to check the clearance between Silk Screen and Fiducial Mark.
  • Added an option in the Fiducial Mark item to check the clearance between inner layer Route Patterns and Fiducial Mark.
  • Added an option in the Acute Angle item to check the angle between the route patterns connected to a circular pad.
  • Added an option in the Acute Angle item to allow violations for fine segments.
  • Added an option in the Metal Mask item to check for area matching between the Metal Mask and Pad.
  • Added an option in the Guide Hole item to check the guide hole size.
  • Added an option in the Hole Distance item to allow overlapped holes where the location is matched.
  • Added an option in the Via Annular Ring item to check the missing Via Pads.
  • Added an option in the Figure Layer item to exclude layer objects within the specific components area.
  • Enhanced algorithm to optimize checking speed of Connected Pattern Direction item.
DFE
  • Added an option to check PAD/VIA when performing a virtual check of Net to Net item.
  • Added an option to set the test criteria as a ratio of the width of the Trace when performing a virtual check of a Net to Net Item.
  • Added an option to allow the consideration of the 'Hole effect' when performing a virtual check of the Power Net to Net item. When this option is used, the ‘Effective Hole Distance’ is used to check the separation distance when a hole exists between two nets.
  • Optimized the verification algorithm of Net to Net item when polygons are designed to overlap, which takes a longer time to merge.
DFE+
  • Enhanced the program to also test 'Composite Power Net' in the IR-Drop check item. This feature allows users to analyze the IR-Drop of the entire power structure combined with passive components, like beads, etc. at once.
  • Added an option to check skew based on Transmission Line Analysis in the Timing Skew Item. This feature allows users to measure timing skew excluding the jitter component.
  • Added an option menu to control the analysis mode for the Timing Skew check item. Using this function, users can analyze Differential Signal in Differential or Common mode.
  • Enhanced the accuracy of impedance analysis of coplanar structures in the Impedance check item. In the previous version, there was a problem with poor accuracy because the ARC's division angle was too large. In this version, the ARC is divided more densely to have a structure that is as similar to the original design as possible, thereby improving accuracy.
  • Improved the result file size of Timing Margin and DDR Compliance Items.
PollEx Manufacturer
Gerber to PCB
  • Added a function to convert the Negative to Positive layers in the Gerber + IPC-D-356 of PCB.
Make Board Paneling
  • Added options to simplify panel board creation and export it to PDF.
PollEx Solver
SI
  • Added an option menu when setting up the buffer model of the EBD model, allows simultaneous setup of multiple pins. Users can use the Assign Device Model Data menu to set up buffer models of multiple pins at once.
  • Enhance the Component data handling method. When importing component data from "PCB", if there is 'Gate Name' information, program is modified to import it as 'Signal Name' information.
PI
  • Enhanced the program to support 'Mil' units during IR-Drop analysis.
  • Enhanced the program to display the PAD of 'Passive Component' in the PIA dialog for better visibility.
  • Added an item to define 'Composite Component' and ‘Source Component’ in the Environment dialog. This allows the user to preset the passive component used in the Composite Net, and the program uses this information to automatically list-up the Composite Nets connected to the Main net in the Select Power Net Pins dialog.
  • Enhance the color data processing method in the IR-Drop analysis result dialog to improve visibility. In the previous version, the Linear interpolation method was used, which made the color map look unnatural, but in this version, the Gradation method is used, which allows for a much more natural color map expression.
  • Modified the program to display Pin Name instead of Source/Port Number when generating PIA from PI.

Resolved Issues

PollEx Modeler
PCB
  • Fixed a bug where the "Display All Redmark Area" feature couldn’t be controlled by category in Redmark.
ECAD Interface
  • Fixed a bug of incorrect material names in the Zuken CR-8000/CR-5000 importer of PCB.
  • Fixed a bug of missing *.rulf extension in the Zuken CR-8000/CR-5000 importer of PCB.
  • Fixed a bug of incorrect Multilayer Pad type recognition in the Altium Designer importer of PCB.
  • Fixed a bug in the Altium Designer importer of PCB where the removed Pads appeared.
  • Fixed a bug in the Siemens PADS importer of PCB where the Copper 2D Line objects are misplaced in the Silkscreen layer.
  • Fixed a bug of incorrect layer stackup and COC Layer in the ODB++ exporter of PCB.
  • Fixed a bug of duplicated texts and unconnected nets in the Altium Schematic importer of Logic.
  • Fixed a bug of missing the Sheet Frame in the Altium Schematic importer of Logic.
PollEx Verification
DFM
  • Fixed a bug in the Fiducial Mark Placement checking option in the Fiducial Mark item.
  • Fixed a bug of missing violations between the route Patterns in the Min Same Net Spacing and Width item.
LDFE
  • Resolved an issue where LDFE's menu structure was different from other tools. Changed some of LDFE's menus to have the same UI structure as other tools.

    DFE: Option/DFE => Verification/DFE

    Redmark: Redmark/Redmark => Collaboration/Redmark

DFE
  • Fixed a bug where the tool would go down during Approach Pair Comp check when the COC line in an Item was created as a line with no width.
  • Resolved issue where the PCB outline was incorrectly applied when checking the Component Position Item. In the previous version, the PCB outline used the Max/Min of the PCB outline, but in this version, it was modified to apply the real PCB outline.
  • Fixed a bug where, in the Copper Cross Over Item, when a Polygon overlaps, this overlap line was judged as a Polygon edge.
DFE+
  • Fixed a bug where the tool would go down when close the PollEx program after performing 'Result Map' in the result window after performing the IR-Drop check item.
  • Fixed an issue where the Net structure of a Coplanar structure was incorrectly applied in the Impedance check item.
PollEx Solver
SI
  • Fixed a bug in Net Topology Analyzer where changing parameters of segment was not reflected in Delay Time.
  • Resolved an issue where the lower Reference Designator was not found properly when using the EBD model in the Network Analysis feature.
  • Resolved an issue where the 'IO type' of each pin was not properly defined when using the EBD model in the Network Analysis feature.