Altair PollEx 2023.1 Release Notes

Highlights

  • Added a new checking item of Conformal Coating in the Tooling category of the DFM.
  • Added a new checking item of Min Same Net Spacing & Width in the Pattern category of the DFM that checks the minimum same net clearance between copper objects and checks the minimum width.
  • Enhanced the classification setting to use the wildcard characters (?, #, and *) when using a string filter.
  • Added a feature to handle variant models in Real PCB Assembly Viewer and Component Arrangement Plan.
  • Enhanced the ODB++ importer to convert a negative to a positive layer.
  • Added a new checking item of 3D Clearance in the Net category of DFE to check the clearance considering component to PCB outline, PCB thickness, and pattern to PCB outline.
  • Added a new checking item of Flight Time in the Signal Integrity category of DFE+ to check the flight time from Driver to receiver between receivers in the driver of the high-speed component.
  • Added a new checking item of Frequency Domain Parameter in the Signal Integrity category of DFE+ to check the return loss, insertion loss, and near-end/far-end crosstalk parameters in the frequency domain.
  • Added an option of Net Topology Analyzer into the Radiated Emission menu of SI to modify the Net Topology (Add Virtual Termination) to perform what-if analysis.
  • Added a feature to draw the “Curved Target Impedance” with three types of Linear, RLC, and RL when setting up target impedance to check the PI PDN analysis results.

New Features

PollEx Modeler
PCB
  • Added a feature to handle variant models in Real PCB Assembly Viewer and Component Arrangement Plan.
PollEx Verification
DFM
  • Added a new checking item of Conformal Coating in the Tooling category.
  • Added a new checking item of Min Same Net Spacing & Width in the Pattern category that checks the minimum same net clearance between copper objects and checks the minimum width.
DFE
  • Added a new checking item of 3D Clearance in the Net category of DFE to check the clearance considering component to PCB outline, PCB thickness, and pattern to PCB outline.
DFE+
  • Added a new checking item of Flight Time in the Signal Integrity category of DFE+ to check the flight time from Driver to Receivers between receivers in the driver of the high-speed component.
  • Added a new checking item of Frequency Domain Parameter in the Signal Integrity category of DFE+ to check the return loss, insertion loss, and near-end/far-end crosstalk parameters in the frequency domain.

Enhancements

PollEx Modeler
PCB
  • Enhanced a feature in Redmark+ to export user-selected area images and allow more detailed markup editing.
Logic
  • Enhanced the Schematic Data Extractor to export a Ref-Pin location.
ECAD Interface
  • Enhanced the ODB++ importer to convert a negative to a positive layer.
PollEx Verification
DFM
  • Added an option in the Layer Stack-up item to check a layer indicator on a board.
  • Added an option in the Hole Distance item to check clearance to a slot NPTH, and to check the PTH/NPTH Clearance to Metal Mask
  • Added an option in the Unrouted Net item to Detect isolated plating holes from the surrounding copper plane (same net).
  • Added an option in the Drill Size of Via item to exclude checking for specific component areas like BGA.
  • Added an option in the Net to Net item to check the clearance between pins (pads).
  • Added an option in the Hole Through Pad item to set a via measure base for the Except Via in Pad Area option.
  • Added an option in the Drill Size of Via item to define a user-defined via using a string filter.
  • Added an option in the Connected Pad item to exclude the patterns to the pad with Thermal Spokes (straight lines that directly connect between the pad and copper polygon, with one pad having two or more straight line patterns connected to it).
  • Added an option in the PSR Covered Via item to define the target VIA using the Padstack string filter.
  • Added an option of the string filter in the Via Spacing2 Item to check clearance between Plugged and S/R Covered Via and Pad.
  • Added an option in the Placement at Reverse Side item to check the clearance between PTH pads and SMD components on the opposite side (soldering side) of the DIP-type components.
  • Added an option in the Drill Scan item to check the missing holes for the PTH.
  • Added an option in the Guide Hole item to check the guide holes based on the board direction.
  • Added an option in the Underfill item to exclude NPTH with the geometry value which is only applicable for the ODB++.
  • Enhanced the Component Placement Angle item result to display the number of base angles.
  • Enhanced the Teardrop item result display to exclude a net.
  • Enhanced the classification setting to use the wildcard characters (?, #, and *) when using a string filter.
  • Enhanced a Base Excel Format export to include the check result status.
  • Modified the Excel result report to open it automatically after the DFx core running.
DFE
  • Added an option of ‘Check the layer based on net structure’ in the Differential Pair Nets item to set in the Separation Check dialog. The purpose of this option is to add evaluation criteria for the inner (Microstrip) and outer (Stripline) layers.
  • Added an option in the Differential Pair Net2 item to give tolerance to the minimum shield distance.
  • Added an option in the Power Net To Net item to search the entire layer for the target object when checking the vertical clearance.
  • Added an option of ‘Display User Selected Item’ in the DFE Environment to display only selected items in the input dialog.
  • Enhanced the algorithm for searching the return path like VOID and Diff coupling in the Return Path item.
  • Enhanced the Component Net Group Excel to search for the net using the “Pin Property”.
  • Enhanced the Detour Length check option in the Power Net to Net item to check the distance of the path along the hole outside if a hole exists between the nets.
DFE+
  • Added an option in the Impedance Check item enabling more accurate inspection by dividing segments based on boundaries when setting the “Component in/out” area instead of checking the entire segment crossing the boundary line.
  • Enhanced the Component Net Group Excel to search for the net using the “Pin Property”.
  • Enhanced the Impedance Check item to allow separate specification of tolerances for the “Main area” and the “Break-In area” when setting up rules for Impedance Check item.
  • Enhanced the target impedance in the PDN Impedance item to use both “linear” and “curved impedances”. The curved impedance is created using the frequency characteristics of R, L, and C elements, and the curve can be reviewed in real-time using the “Display” button."
  • Modified the measurement result display method in the DDR Compliance item to enable setup using the Eye-Mask Parameter in the case of memory verified with Eye-Mask.
Technical Cleanliness
  • Added an option to export use-selected area to ODB++ format.
  • Enhanced the hazardous area analysis algorithm.
PollEx Solver
SI
  • Added an option in the Network Analysis to select the “Standard Eye-Mask” from the list.
  • Added an option of Net Topology Analyzer into the Radiated Emission menu of SI to modify the Net Topology (Add Virtual Termination) to perform what-if analysis.
    Limitation:
    • In this function, only Virtual Termination (R/L/C) can be added to the Driver/Receiver pin. Components cannot be added/removed anywhere other than the Driver/Receiver stage.
    • The value of passive components included in Net cannot be changed.
  • Enhanced the Network Analysis to use components with non-linear characteristics such as FET or Transistor. The simulation model of the Non-Linear Component supports the Spice model. This version does not support cases containing multiple elements in the same package.
    Limitation:
    • In this version, only analysis of non-linear devices connected to signals is possible. Non-Linear Device analysis function for component connected to Polygon is scheduled to be developed in the future.
    • In this version, only analysis of single package is possible. Analysis is not possible if multiple components are included in one package. This feature will be developed in the future.
    • In this version, support ".subcircuit" type SPICE model only.
  • Enhanced the Automatic DDR Bus analysis report to include “Eye-Mask Parameter” information.
PI
  • Added a feature to draw the “Curved Target Impedance” with three types of Linear, RLC, and RL when setting up target impedance to check the PDN analysis results.
  • Modified the Port selection method to ensure that when a Load Pin is chosen for the IR-Drop analysis of a Composite Power Net, the Source Pin is automatically deselected to prevent user mistake.
PollEx Manufacturer
Mounting Emulator
  • Added an option to support variants to display variant models and to export coordinates of variants.

Resolved Issues

  • Fixed a bug in Altium Schematic importer in Logic to recognize some net information correctly when the unit is a millimeter.
  • Fixed a bug in the Export Result Table in the DFM Routing Slit item to export the Routing_Slit_Via checking.
  • Fixed a bug of the pad existence check in the DFM DIP Annular Ring item in case of missing draw objects in the Padstack library.
  • Fixed a bug in the Impedance Check item of DFE+ that different tolerances can be assigned to the Main and Sub areas when setting the tolerance of Target Impedance.
  • Fixed a bug displaying incorrect results in the Logic DFE’s Exist Net item.
  • Fixed a bug in the Network Analysis of SI not properly recognize the buffer model when using the EBD model in the existing version.
  • Resolved an issue of differential pair net highlight in Net Topology Analyzer to work the coupling function between differential pair pins when using the EBD model in the existing version.