Altair PollEx 2024.1 Release Notes

Highlights

PollEx Modeler
PCB
  • Added a feature to support variant(*.lst) file in the Cadence Allegro importer.
UPE
  • Added a function to import the UPF libraries from the Ultra Librarian in the File > Import menu.
PollEx Verification
Technical Cleanliness
  • Added the Exposed Copper option (set to the default option) to the Calculation Method in the Technical Cleanliness analysis input dialog.
  • Enhanced the hazard area calculation algorithm for more accurate results.
PollEx Solver
PI
  • Added a slide menu to change the voltage range in the IR-Drop analysis result image for adjusting the display voltage range dynamically.
SI
  • Resolved the Timing measurement failure by centering the strobe signal’s cross point in the display window for Automatic DDR Bus analysis instead of the data signal’s cross point, which caused timing measurement issues related to the operating frequency.

New Features

PollEx Verification
Technical Cleanliness
  • Added Technical Cleanliness environment to set the default Layer/Highlight color and Link to ECAD option.

Enhancements

PollEx Modeler
PCB
  • Added an option to define the copper etching factor of the layer stack-up in the PCB environment.
  • Added Via aspect ratio (length/hole diameter) information in the Padstack/Via Viewer.
  • Added Navigate to the current design path in the File menu.
  • Modified the outdated ECAD names in the Import ECAD menu.
  • Enhanced the Auto-Update function in the PCB environment to recognize the latest installer by comparing the digital signature.
ECAD Interface
  • Added a command option to support the variant file (*.dst) in Zuken CR-8000/CR-5000 importer.
  • Enhanced COC layer set-up to support multiple layers in the PADS importer.
  • Enhanced the layer stack-up information for the materials and copper etching factor in SIWave exporter.
PollEx Verification
DFM
  • Added an option in the Hole Distance item to define the target objects using Padstack String Filter.
  • Added an option in the Conformal Coating item to define the non-coated layers.
  • Added an option in the Conformal Coating item to check the clearance between the coated area and Panel edges, Test Point, and non-coated Area.
  • Added an option in the Fiducial Mark item to define the target objects using a Padstack String Filter.
  • Added an option in the Silver Paste TH PCB item to check Clearance to the pattern. (Other Net)
  • Added an option in the Test Point2 item to check the clearance between the Test Point and components based on the component height.
  • Added an option in the Screw2 item to exclude pattern areas that overlap with component pads or copper polygon.
  • Added an option in the Data Existence item to check whether the specific layers exist in the footprint library.
  • Added an option in the Dip Annular Ring item to define the target layers.
  • Added an option in the Silk to Silk item to exclude specific components.
  • Added an option in the Copper Connected Pad item to define the target layer for the DIP pad.
  • Added an option in the BGA item to define the tolerance of the PTH Via location between BGA pads.
  • Added an option in the Via Spacing2 item to except the directly connected Vias with the same net.
  • Enhanced the result display of the Solder Resist Pad item to display the solder mask object with hatched highlight.
  • Enhanced the checking algorithm in the Under Hole/Via item to detect the slit hole width violations under the specific component area.
  • Enhanced the checking algorithm in the Screw2 item to recognize only through-hole type objects as the screws.
  • Changed the target layer term from All Layers to Both in the Fiducial Mark item.
LDFE
  • Added an option to define the PIN Type in the Duplicated Output Net item.
  • Added an option to assign a simulation model path in the Transient Stress Test item
  • Added a component information column in the result table of the Pair Comp item.
  • Enhanced the Schematic Data Extractor function to include Pin Type information.
DFE
  • Added an option to skip checking the presence of a Reference Ground at the layer below the Pin Pad in the Component Shield item. When this option is enabled, only the fill-cut of the pin pad is checked and the presence of the reference ground below it is not checked.
  • Added an option to set the default Check Mode for the Power Net to Net item. This option allows to apply either Clearance Mode or Expand Mode as the default for all sub-items.
DFE+
  • Added an option to overwrite the previously set Net Class information when running the Find Net Class menu.
  • Added an option of Analysis Type in the Timing Skew item whether to perform the skew check on an Eye-Diagram or a Waveform.
  • Added a Show All menu in the Crosstalk Noise item to review the crosstalk coefficients of all nets.
  • Added an option to use both Value and Ratio for setting the Safety Margin in the DDR Compliance item.
  • Enhanced the Timing Skew item to record the length difference between two nets in the skew check result window for measuring the delay time skew between nets.
  • Enhanced the Timing Skew item to allow the single-ended signal to be used as a Strobe Net when checking the Strobed Bus Skew.
  • Enhanced the Timing Skew item to automatically set the Simulation Time based on the Operating Frequency during waveform analysis.
  • Enhanced the Impedance item to support the Real Mode for analyzing the impedance of the Differential Pair Net.
Technical Cleanliness
  • Enhanced the analysis algorithm to calculate the hazard area between the pads after the next within a component.
  • Enhanced the analysis performance speed.
  • Enhanced line thickness for the Set Area function in the Technical Cleanliness.
PollEx Solver
PI
  • Enhanced the setup process for Composite Net when configuring PIA for PI PDN analysis by consolidating the setup into a single screen.
  • Enhance the PIA dialog to display the PAD of the Composite Component.
  • Enhanced the PIA dialog to display the Pin Name of the component instead of the Port number, which was displayed in the previous version.
SI
  • Added an option to prompt to confirm whether to overwrite the previously set Net Class information when running the Find Net Class menu.
  • Enhanced the Transmission Line Analysis feature to support the Real Mode for impedance analysis of Differential Pair Net.
  • Enhanced the setup process of the Electrical & Thermal Properties dialog for configuring all necessary parameters automatically when the EBD model is assigned. The MCP Reset button in the Electrical & Thermal Properties dialog has been removed. In the previous version, the related parameters were set up only after clicking this button post-EBD model assignment.
  • Enhanced the Electrical & Thermal Properties dialog to automatically populate the Signal Name/Pin Type field in the table when the EBD model is assigned.

Resolved Issues

PollEx Modeler
Logic
  • Fixed a bug of missing the logic symbol shapes in the Symbol Viewer.
ECAD Interface
  • Fixed a bug of misaligned components when importing the ODB++ data created from the Cadence Allegro PCB.
  • Fixed a bug of component text mirroring in the Zuken CR-8000/CR-5000 importer of PCB.
  • Fixed a bug of the unrecognized component heights of the keep-out objects in the PADS importer of PCB.
  • Fixed a bug of the unrecognized non-plated holes in the Cadence Allegro importer of PCB.
  • Fixed a bug in the Zuken CR-8000/CR-5000 importer of PCB where components placed on the bottom layer were recognized as broken libraries.
  • Fixed a bug of incorrectly displayed symbols in the Altium Schematic importer of Logic.
  • Fixed a bug of duplicated components and texts in the Altium Schematic importer of Logic.
PollEx Verification
LDFE
  • Fixed a bug of not properly finding the net connected to the component pin in the Connected Pins item.
DFE
  • Resolved the issue of incorrectly recognizing polygon boundaries by modifying the program to merge and test the polygons in the Copper Crossover Detect item.
  • Resolved the issue of incorrectly recognizing the overlap status of nets when checking vertical overlap between nets in the Net to Net item.
  • Fixed a bug where the fill cut check was not performed properly when the component was placed at an angle in the Component Shield item.
DFE+
  • Fixed a bug that may not measure Flight Time when there was a voltage offset in the waveform of the Driver and Receiver in the Flight Time item.
  • Fixed a bug where ARC objects were displayed incorrectly in the impedance measurement result image in the Impedance Check item.
  • Fixed a bug that the error net is not highlighted properly in the case of Composite Net when clicking on the error item in the result table in the Timing Skew item.
  • Fixed a bug where Flight Time was measured incorrectly according to the set Operating Time in the Timing Skew item.
  • Fixed a bug in incorrect measurement when the Driver/Receiver waveform is crossed in the Flight Time item.
  • Fixed a bug where VSEL/VSEH of the DQS signal was not checked in the DDR Compliance item. In previous versions, VSEH/VSEL was measured only for the clock signal.
Technical Cleanliness
  • Fixed a bug that incorrectly measured target pads within a component.
PollEx Solver
SI
  • Resolved a bug that the tool crashes when analyzing multiple nets during Network Analysis.
  • Resolved the Timing measurement failure issue to modify the program so that the cross point of the strobe signal, which is the standard point for timing measurement is located in the exact center of the display window in the Automatic DDR Bus Analysis feature. In the previous version, the cross point of the data signal was located in the center of the window, so there was a problem with timing not being measured properly according to operating frequency.
  • Resolved an issue where tool down occurred frequently during the EBD model assign process in the Parts menu.
  • Resolved a bug of Net Topology not being created properly when using the EBD model in the Net Topology Analyzer menu.