Altair PollEx 2025.1 Release Notes

PollEx Verification

PollEx Solver

• PI
  • Enhanced the accuracy and performance of the IR-Drop Solver by replacing the mesher.
• Thermal
  • Added an option to set the Number of Convergence Iterations to the Thermal Analysis Constraints, allowing control of the iteration count.

New Features

PollEx Verification

• LDFE
  • Added a Composite Power Net Option to the Standard Net Name item in the Component category.

PollEx Solver

• SI
  • Added a Net Topology Viewer menu accessible via the right-click context menu in the Automatic DDR Bus Analysis, enabling review of the net structure before performing the analysis.

PollEx Manufacturer

• Make Board Paneling
  • Enhanced functionality to simplify the creation of panel boards.
  • Added functionality to export designs in both PDF and DXF formats.

Enhancements

• PCB
  • Enhanced the result report format for the Comp Placing Density of Component Arrangement Plan.
  • Enhanced the STEP exporter to recognize a closed PCB outline as a cutout hole in the Real PCB Assembly Viewer.
  • Modified the Current Unit display format in the Unit Conversion dialog.
• Logic
  • Added a notice when opening a SDBB file that contains duplicate reference names.
  • Improved the list table and search features in the Symbol Viewer dialog.
  • Enhanced SDBB file saving functionality to support duplicate reference names.

• Reorganized the Import from Altium Designer window for PCB.
• Enhanced the Define ECAD Part Name option to recognize the ECAD Part Name from Design Item ID information in the Import from Altium Designer window for PCB.
• Enhanced the Layer Stack feature to support multiple dielectric layers between copper layers in the Import from Cadence Allegro window for PCB.
• Enhanced the Layer Stack feature to support multiple dielectric layers between copper layers in the Import from ODB++ window for PCB.
• Added an option to define the ECAD Part Name and the PCB Design Name in the Import from ODB++ window for PCB.
• Added an option to set the COC line width to zero in the Import from ODB++ window for PCB.
• Added an option to set user-defined layers for the COC layers in the Import from ODB++ window for PCB.
• Added an option to set user-defined layers for the Board Outline and Hole(Drill) in the Import from IPC-2581 window for PCB.
• Enhanced the Import from IPC-2581 window for PCB to optimize the Revision A and B formats exported from Cadence Allegro.
• Added a Connected Net Info property for TieBar objects to the Import from Siemens Xpedition window for PCB.
• Enhanced the Import from Altium Designer window for Logic to automatically import Block (Child) sheets used in the main sheet.
• Enhanced the Import from Altium Designer window for Logic to display the Block Symbol and Block (Child) sheets.
• Enhanced the Import from Altium Designer window for Logic to handle components with duplicate pin names by appending lowercase letters (e.g., a, b, c...) to distinguish and import all pins.

• DFM
  • Added an option in the Mechanical Short item to check the overlap between the figure patterns and other single-net objects.
  • Added a Measure Base option to check the remainder components clearance for the PCB Outline Spacing item.
  • Added an option to check the clearance based on the component height in the PCB Outline Spacing item.
  • Added an option in the PCB Outline Spacing item to check the distance between the PCB outline and the Solder Mask Edge inside the PCB board area.
  • Added an option in the Solder Resist Pad item to except pattern violations which are directly connected to the pad inside of the figure Solder Mask area.
  • Added an option in the Hole Through Pad item to exclude specific components.
  • Added an option in the PSR Covered Via item to exclude specific components.
  • Added an option in the Text Existence item to check the distance between the Pin connected to the target net and the defined text.
  • Added an option in the Placement item to define the Keep In/Out area from the COC area of the component.
  • Added an option in the Placement Keepout item to check the clearance based on the percentage of the component's height.
  • Added an option in the Placement Keepout item to exclude the pads connected with the defined net.
  • Added an option in the Silk on Pad item to exclude silkscreen objects with zero width.
  • Added a Metal Mask option in the Measure Base list of the Screw2, Mark Placement, Component Spacing 2, Routing Slit, and PCB Outline Spacing items.
  • Enhanced the Pad Inside option of the Measure Base in the Keep Out Pattern item to recognize the inner area of two-row QFN and QFP components.
  • Enhanced the Solder Mask Clearance option in the Placement Keepout item to support separate clearance values ​​for components and board figures.
• DFA
  • Optimized algorithm to shorten the verification time for the Shadow Region item.
• LDFE
  • Enhanced the Comp/Net Group Excel handling method to allow selection of the creation result by Part Name or Reference Name when creating a Component Group using Comp/Net Group Excel.
• DFE
  • Added an option to the Consider entire Polygon connected by Trace for the Stability Copper item to check vias across the whole structure when polygons are connected through traces.
  • Enhanced the measurement method in the ARC section of the Power Width item to ensure optimal results.
  • Optimized the verification time of the Diff-Complete Shield item by improving the ground net merge process.
• DFE+
  • Enhanced the Timing Skew item to support checking relative skew in addition to absolute skew. The updated functionality enables separate analysis of early-arriving skew and late-arriving skew, addressing limitations in previous versions that only measured absolute skew values.
  • Improved the input file import process by detecting and updating changes in Component and Net Groups, enabling the same input file to be reused across multiple designs.
  • Improved the Input window to allow detailed buffer model setup for individual nets. Configurations were limited to the net group in previous versions.
  • Improved the DFE+ core option to check the suitability of PCB layers when performing analysis.
  • Modified the Flight Time item to account for via delay in delay time calculations.
  • Clicking Analyze on the Timing Skew item now opens the Net Topology Analyzer with timing parameter details for each segment, simplifying result analysis .

Resolved Issues

PollEx Modeler