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PollEx User Guides
Discover PollEx functionality with comprehensive user guides.
Verification User Guides
This section contains the user guides for the following tools: DFA, DFE, DFE+, DFM, and Logic DFE.
DFM
PollEx DFM is a board level manufacturability checking software.
Check Item Category
PAD
Via Spacing 2
Check via clearance depending on via size.

Welcome
What's New
View new features for PollEx 2024.1.
Get Started
Learn the basics and discover the workspace.
PollEx Tutorials
Discover PollEx functionality with interactive tutorials.
PollEx User Guides
Discover PollEx functionality with comprehensive user guides.
- Manufacture User Guides
  This section contains the user guides for the following tools: Block JIG Generator, Compare GDSII, Gerber to PCB, Make Board Paneling, Metal Mask Manager, Mounting Data Extractor, Mounting Emulator, Router-Machine JIG Generator, Solder Quantity Calculator, Soldering Pallet, Test Point Location Generator, and Underfill.
- Modeler User Guides
  This section contains the user guides for the following tools: BOM, CAM, Component Arrangement Plan, CP, Golden Sample, Logic, PCB, Redmark+, and Worksheet Planner.
- Solver User Guides
  This section contains the user guides for the following tools: PI, SI, SI Explorer, and Thermal.
- Verification User Guides
  This section contains the user guides for the following tools: DFA, DFE, DFE+, DFM, and Logic DFE.
  - DFA
    PollEx DFA is an assembly status checking toolset for PCB design based on 3D package library.
  - DFE
  - DFE+
    PollEx DFE+ is a fully automated SI analysis tool.
  - DFM
    PollEx DFM is a board level manufacturability checking software.
    - Start DFM
      From the menu bar, click Option > DFM > Input after reading the design file to make a DFM input file.
    - Component Classification
    - Check Item Category
      - Board
      - Component
      - Drill Size
      - Etc.
      - FPCB
        FPCB is excellent for development of electronic components as electronic appliances are becoming miniaturized and lightweight.
      - Ground Wall
        Check the clearance for an area affected by ground wall.
      - Package
      - PAD
        Copper Connected Pad
        Check specified components pattern connected pin area ratio.
        Copper Keep-out Around Pad
        Dummy Pad
        Check existence of dummy pads.
        Dummy Pad2
        Check different type of dummy pad existence in design.
        Hole Through Pad
        Check holes placed on component pads.
        Metal Mask
        Check the metal mask design rules.
        Minimum Via Land Size
        Check size of Via's land.
        Multiple Pattern Connect
        Check target component’s pattern connecting status.
        PSR Covered Via
        Check Vias are covered with PSR or solder mask.
        Silk on Pad
        Check if silkscreen data are overlapped with pads.
        Solder Resist Pad
        Solder Resistor (SR) is a material which is applied to specific areas of the printed circuit board during a soldering process and protects the circuit of the unnecessary portions of solder.
        Teardrop
        Check rule related to teardrop in design.
        Thermal Pad
        Check rule for component thermal pads.
        Via Annular Ring
        Check the annular ring, the distance between pad and HOLE size.
        Via Overstack
        Check the number of layers for drilling operation.
        Via Spacing
        Depending on the via type, check different clearance to different PCB objects.
        Via Spacing 2
        Check via clearance depending on via size.
        Via S/R Spacing
        Check the distance between solder mask in via to other pads.
        Wave Mark
        Check wave mark in the FPC component edge.
      - Pattern
      - Placement
      - Test Point
        Verify if the clearance between test points and other objects follow specifications and if the test points contain text.
      - Test Point2
        Analyze the clearance between a test point and each component on a board.
      - Tooling
      - Underfill
        Find and examine underfill areas in BGA-type components.
    - Result
    - Lock Input Setup
      Lock the DFM input rule file (*.DFMI) to prevent any modifications from others.
  - Logic DFE
    PollEx Logic DFE is a toolset that checks electrical validity and standardizing of schematic design.
  - Technical Cleanliness
    PollEx Technical Cleanliness (TC) is an optional module of the PollEx PCB and a reliability analysis tool set for hazardous areas on a PCB design, using its micro particles.
- UPE User Guides
  This section contains the PollEx UPE user guide.
PollEx Installation Guide
Instruction to install PollEx 2024.1.
Character String Search Rule
Definition for meta character using in making sentence for searching option.

Via Spacing 2

Check via clearance depending on via size.

Via Class Definition: Define the via information such as type, hole size, and measurement base with clearance value. It is possible to add the via class on the list by clicking Add Via Class.
- Via Class Name: Specify the Via Class name.
- Via Type: Define the type among All, Through Via, Blind Via, Buried Via, Via Padstack, and Via String Filter. Via type will be detected automatically following PCB design information.
- Hole Size: Define via hole size such as certain value or range.
  - Via Padstack: In case of via Padstack, it can select via from the padstack list dialog if you choose this. (Click the Hole Size menu to be enable this.)
- Measure Base: Select one of two items between pad shape and hole shape. This will be used to measure the clearance from other objects to via.
  Figure 1.
  - Pad Shape: Via pad outer shape will be used as via boundary.
  - Hole Shape: Via hole will be used as via boundary.
Clearance to Via: To check the clearance between via to via. Each combination will be generated automatically by clicking Default Reset. Clearance value will be defined by getting Via Class Definition, and you can change or define the measure base with each clearance value.
- Exception: Clearance between same net vias is excluded from verification when specific conditions are met.
  - If two measurement points are located within the Copper or Pattern, they are excluded from the validation.
  Figure 2.
- - Keep Other Values while Adding new Classes Combination: To keep the previous setting when adding a new via Class, select this option.
Clearance to PAD: To check the clearance between via to PAD of component. Select Component Group and then select Via Class. Measure base can be defined here with clearance value depend on target net such as SMD (Same Net), SMD (Other Net) and DIP (Same Net), DIP (Other Net).