Welcome
What's New
View new features for PollEx 2025.
Get Started
Learn the basics and discover the workspace.
PollEx Tutorials
Discover PollEx functionality with interactive tutorials.
PollEx User Guides
Discover PollEx functionality with comprehensive user guides.
- Manufacture User Guides
  This section contains the user guides for the following tools: Block JIG Generator, Compare GDSII, Gerber to PCB, Make Board Paneling, Metal Mask Manager, Mounting Data Extractor, Mounting Emulator, Router-Machine JIG Generator, Solder Quantity Calculator, Soldering Pallet, Test Point Location Generator, and Underfill.
- Modeler User Guides
  This section contains the user guides for the following tools: BOM, CAM, Component Arrangement Plan, CP, Golden Sample, Logic, PCB, Redmark+, and Worksheet Planner.
- Solver User Guides
  This section contains the user guides for the following tools: PI, SI, SI Explorer, and Thermal.
- Verification User Guides
  This section contains the user guides for the following tools: DFA, DFE, DFE+, DFM, and Logic DFE.
  - DFA
    PollEx DFA is an assembly status checking toolset for PCB design based on 3D package library.
  - DFE
    - Input Setup
    - Object Group Setting
      Group the same type of objects into the same group.
    - DFE Items
      - High Speed
      - Differential Pair Net
      - Net
        Allowed Pattern Width
        This rule checks whether nets keep allowable trace widths.
        3D Clearance
        Antenna Via
        Bus
        Bus2
        BUS (T-Topology)
        Component to Net Clearance
        This rule checks for component clearance violations when routed traces may affect the performance of nearby components.
        Confirm Net Group
        This option helps engineers to visually differentiate specific classes of nets or net groups from the rest of nets, and identify nets with more or less than the specified number of connected components.
        Connected Comp
        This rule checks for the proper use of special purpose components.
        Connected Circuit
        This rule checks for the validity of circuit usage and whether the routing length and clearance from driver pins are within the specified distance.
        Copper Area Ratio
        This item checks for copper area ratio on each layer.
        DC Resistance
        In high power system the designer should check trace resistance in order to avoid IO-Drop problem. This rule calculates trace resistance.
        GND Isolation
        Length
        This rule checks for a trace length violation.
        Limit Approach Net
        This rule checks whether two nets are within a specified distance.
        Net Loop
        This item checks whether the net has formed a loop.
        Net Group Shield
        This item checks for a shielding ratio of bus group.
        Net Isolation
        This item checks net connection between start pins to end pins.
        Net Self Coupling
        This item checks whether the same net is placed close together.
        Net to Net
        This item checks whether a specified clearance requirement for the net is satisfied.
        Passive Device Stability
        This item checks whether the filter installed in the IO terminal is well designed with low impedance.
        Pattern Sharp Angle
        This rule searches for routing angles that are sharper than the specified reference angle.
        Prohibited Connected Comp
        This item finds components that should not be connected to certain signals.
        Serpentine
        This item checks all symmetry items for uniformity of the differential pairs design environments.
        Star Connection
        This rule checks whether power pin connected to decap via separation path to form a Star Connection.
        Stub
        This stub rule checks unnecessary stubs for specific use cases.
        Test Point
        This rule checks the test point/via number and clearance of net.
        Net Topology
        This item checks whether the topology required for design is used.
        Via Quantity
        This item checks layers change by counting the number of Vias used in a signal net.
        Width
        This rule checks routed trace widths against the specified minimum or maximum allowable widths.
      - Power
      - Filter
      - Component
      - Board
    - DFE Environment
      View DFE Environment setting methods.
    - Result
  - DFE+
    PollEx DFE+ is a fully automated SI analysis tool.
  - DFM
    PollEx DFM is a board level manufacturability checking software.
  - Logic DFE
    PollEx Logic DFE is a toolset that checks electrical validity and standardizing of schematic design.
  - Technical Cleanliness
    PollEx Technical Cleanliness (TC) is an optional module of the PollEx PCB and a reliability analysis tool set for hazardous areas on a PCB design, using its micro particles.
- UPE User Guides
  This section contains the PollEx UPE user guide.
PollEx Installation Guide
Instruction to install PollEx 2025.
Character String Search Rule
Definition for meta character using in making sentence for searching option.

Allowed Pattern Width

This rule checks whether nets keep allowable trace widths.

In analog design, signal impedance is not an important factor in routing and signal trace widths are decided depending on allowable current values. Assuming PCB layer thickness remains the same, trace width is a main factor in deciding current carrying capability of the trace.

Item: Input item name.
Net: Select a target net group.
Limit: Select allowable value type between Min, Max and Middle.
Tolerance(%): Input allowable trace width ratio relative to the Limit Width.
Limit Width: Assign a reference trace width (Limit Width).

Trace Width and Current Carrying Capacity

When current flows through a conductor, it will heat up due to I2R losses. Larger cross section (for example, wider and/or thicker) traces exhibit less resistance and therefore less heating.

To determine the minimum trace width required to minimize heating, determine the maximum current a trace will carry and the thickness of the copper you will use on PCB.

The minimum trace width is expressed as:

Figure 1.

Figure 2.

w = (\frac{1}{1.4 \times h}) \times {(\frac{I}{k \times Δ T^{0.421}})}^{1.379}

$w = (\frac{1}{1.4 \times h}) \times {(\frac{I}{k \times Δ T^{0.421}})}^{1.379}$

(Derived from the IPC-2221A standard)

Where,

$w$ $w$: Minimum trace width, mils.
$h$ $h$: Thickness of copper layer, oz/ft².
$I$ $I$: Current load of the trace, A.
$k$ $k$: 0.024 for inner layers.; 0.048 for top and bottom layers.
$Δ T$ $Δ T$: Maximum permissible rise in temperature (Celcius) of the conductor above ambient temperature.