This section contains the user guides for the following tools: Block JIG Generator, Compare GDSII, Gerber to PCB,
Make Board Paneling, Metal Mask Manager, Mounting Data Extractor, Mounting Emulator, Router-Machine JIG Generator,
Solder Quantity Calculator, Soldering Pallet, Test Point Location Generator, and Underfill.
This section contains the user guides for the following tools: BOM, CAM, Component Arrangement Plan, CP, Golden Sample,
Logic, PCB, Redmark+, and Worksheet Planner.
View editable, versatile control parameters which influence the simulation/analysis results for crosstalk, network,
electromagnetic field, eye-diagram, and SPICE.
Validate the design decisions throughout the design process including the selection board layer stack-up, placing
decoupling capacitors on the board, and routing power/ground nets.
To perform PI analysis, you must assign target power net, source pin, load pin, and
ground pin.
From the menu bar, select Analysis > Power Integrity.
The Select Power Integrity Analysis Model
opens.
Select a power net.
the selected Power Integrity Analysis Model name is displayed in the
window. You can remove a model by clicking
Remove.
Assign the target power net in one of the following ways:
Select Power Pins: Assign target power
net by selecting required power net from power net list. This method is
provided for normal PDN and IR-Drop analysis.
Select Signal Nets: Assign target
power net by selecting signal nets. This method is provided for SSN
analysis.
Select Power Pins
Assign the target power net for PI Analysis by selecting power pins.
Select Signal Nets
Assign the target power net for PI Analysis by selecting signal nets.
Power Integrity Analyzer
Validate the design decisions throughout the design process including the selection board layer stack-up, placing decoupling capacitors on the board, and routing power/ground nets.