Processing math: 100%

Welcome
What's New
View new features for PollEx 2025.
Get Started
Learn the basics and discover the workspace.
PollEx Tutorials
Discover PollEx functionality with interactive tutorials.
PollEx User Guides
Discover PollEx functionality with comprehensive user guides.
- Manufacture User Guides
  This section contains the user guides for the following tools: Block JIG Generator, Compare GDSII, Gerber to PCB, Make Board Paneling, Metal Mask Manager, Mounting Data Extractor, Mounting Emulator, Router-Machine JIG Generator, Solder Quantity Calculator, Soldering Pallet, Test Point Location Generator, and Underfill.
- Modeler User Guides
  This section contains the user guides for the following tools: BOM, CAM, Component Arrangement Plan, CP, Golden Sample, Logic, PCB, Redmark+, and Worksheet Planner.
- Solver User Guides
  This section contains the user guides for the following tools: PI, SI, SI Explorer, and Thermal.
- Verification User Guides
  This section contains the user guides for the following tools: DFA, DFE, DFE+, DFM, and Logic DFE.
  - DFA
    PollEx DFA is an assembly status checking toolset for PCB design based on 3D package library.
  - DFE
    - Input Setup
    - Object Group Setting
      Group the same type of objects into the same group.
    - DFE Items
      - High Speed
        AGND/Power-Net Clearance
        This item reports problems when low frequency power and high frequency signal traces are routed too close to each other.
        Approach GND VIA (Stitching Via)
        This item checks whether high speed signal vias have their ground vias as shielding within a certain region.
        Approach Prohibition Via
        This item checks for high speed signal’s inner via structure.
        Complete Shield
        This item checks for a shielding ratio on design. Ground shielding should consider the effect on impedance change.
        Copper Cross Over Detect
        Routing Area Ratio
        Component providers can guide their products’ signal connection specification as topology style, impedance or delay time control.
        Via Inductance
        Via Capacitance
        Return Path
        Plane Edge Coupling Check
      - Differential Pair Net
      - Net
      - Power
      - Filter
      - Component
      - Board
    - DFE Environment
      View DFE Environment setting methods.
    - Result
  - DFE+
    PollEx DFE+ is a fully automated SI analysis tool.
  - DFM
    PollEx DFM is a board level manufacturability checking software.
  - Logic DFE
    PollEx Logic DFE is a toolset that checks electrical validity and standardizing of schematic design.
  - Technical Cleanliness
    PollEx Technical Cleanliness (TC) is an optional module of the PollEx PCB and a reliability analysis tool set for hazardous areas on a PCB design, using its micro particles.
- UPE User Guides
  This section contains the PollEx UPE user guide.
PollEx Installation Guide
Instruction to install PollEx 2025.
Character String Search Rule
Definition for meta character using in making sentence for searching option.

Via Capacitance

Via capacitance is calculated as:

$C = \frac{0.55 ε_{r} T D_{1}}{D_{2} - D_{1}}$

Where,

$D_{2}$: Diameter of clearance hole in the ground plane [cm]
$D_{1}$: Diameter of pad surrounding via [cm]
$T$: Thickness of PCB [cm]
$ε_{r}$: Relative electric permeability of PCB material
$C$: Parasitic via capacitance [pF]

Consider a signal coming from back side of the board to the topside of the board through a via. $T$ = 0.157 cm thickness board, $D_{1}$ = 0.071 cm, $D_{2}$ = 0.127 cm.

$C$ = 0.51pF