Plane Edge Coupling Check

When the ESD current flows along the GND Plane, a large noise is formed at the point where the impedance of the GND Plane is high, and as a result, a large noise is coupled to the surrounding net. Usually, the impedance around the VIOD or around the edge of the plane is relatively high, causing a lot of ESD noise. This Item checks whether the target Net is Routing near the VOID or Plane Edge.

• Target Nets: Select target net group
• Test Condition:
  • Distance from plane edge(M/S): Maximum separation distance between Microstrip and Plane Edge.
  • Distance from plane edge(S/L): Maximum separation distance between Strip line and Plane Edge.
  • Distance from VOID edge: Maximum separation distance between Net and VOID edge.
  • Allowable maximum trace length: The maximum allowable length of the net close to the plane edge or VOID edge.
  • Target Layer: Select the required test layer. (All/L1 Layer/L2 Layer)
• Options
  • Pin Escape: Enter a radius of circular region around pins to be excluded for the rule check.
  • Via Escape: Enter a radius of circular region around vias to be excluded for the rule check.
  • Include PIN/PAD/Copper: DFE checks net separation include PIN/PAD/Copper.
  • Include VOID edge(min area): The minimum area of the VOIDE to be tested. VOID with an area smaller than this area is excluded from the test.
  • Merge Polygon: If you use this option, test after merging all polygons.