DDR Compliance

This item checks the followings:

• The setup time margin(pS) of DDR memory system.
• The hold time margin(pS) of DDR memory system.
• The tDQSQ time margin(pS) of DDR memory system.
• The tQH time margin(pS) of DDR memory system.
• The overshoot voltage margin(mV) of DDR memory system.
• The overshoot area margin(V-nS) of DDR memory system.
• The undershoot voltage margin(mV) of DDR memory system.
• The undershoot area margin(V-nS) of DDR memory system.
• The VSEH Margin(mV) of DDR memory system.
• The VSEL(mV) margin of DDR memory system.
• The VIX margin(mV) of DDR memory system.
• The VID margin(mV) of DDR memory system.

• Item: Sub item name. User can enter arbitrary name.
• Net Group: Select target net groups to be tested. Allow multiple net groups.
• Strobe Net: Option to select target strobe net groups to be tested. (Clock, DQS, etc.)
• Setup Margin(pS): Enter required minimum setup time margin value in pS unit.
• Hold Margin(pS): Enter required minimum hold time margin value in pS unit.
• tDQSQ Margin(pS): Enter required maximum tDQSQ time margin value in pS unit.
• tQH Margin(pS): Enter required maximum tQH time margin value in pS unit.
• Overshoot Margin(mV): Enter allowable maximum overshoot voltage in mV unit.
• Overshoot Area Margin(V-nS): Enter allowable maximum overshoot area amount in V-nS unit.
• Undershoot Margin(mV): Enter allowable maximum undershoot voltage in mV unit.
• Undershoot Area Margin(V-nS): Enter allowable maximum undershoot area amount in V-nS unit.
• VSEH Margin(mV): Enter allowable minimum single-ended high level voltage of differential signal in mV unit.
• VSEL Margin(mV): Enter allowable maximum single-ended low level voltage of differential signal in mV unit.
• VIX Margin(mV): Enter maximum allowable crosspoint deviation value of differential signal. (DDR3)
• VID Margin(mV): Enter maximum allowable crosspoint deviation value of differential signal. (DDR2)
• Analysis option: Upon double-clicking this field, the Automatic DDR Bus Analysis dialog will be displayed. This dialog is used for automatically extracting all data strobe, data, clock, address, command, and control line nets of DDR (double data rate) memory interfaces including DDR (DDDR1), DDR2, DDR3 and DDR4, automatically constructing data line, address line, command line, and control line analysis models, performing eye diagram analyses on all of the models, and calculating the setup and hold timing margins of all data, address, command, and control line signals.

There are two ways to assign the simulation buffer model:

• Use pre-defined buffer model: The buffer model set in the electrical pin part of UPE is used as default. You cannot change the buffer model here.
• Use user defined buffer model: You can assign simulation buffer model.

• DDR Bus Nets: All automatically extracted DQS, DQ, CLK, ADD, CMD, and CTRL nets are listed. You should review the extracted net names and make corrections as needed by adding nets, removing nets, or changing the net types. For DQS and DQ nets correct byte lane numbers must be assigned.
• Device Model: You can assign driver/receiver buffer simulation model, driving strength of driver and other simulation parameters. There are two ways to assign the simulation buffer model:
  • Use pre-defined buffer model: The buffer model set in the electrical pin part of UPE is used as default. You cannot change the buffer model here.
  • Use user defined buffer model: You can assign simulation buffer model. The default buffer model is initially assigned to the buffer model field which can be changed by users. When the device models are not available in the part data, the default linear device models defined here are used for transient simulation of signal integrity analyses. For the DQS and DQ nets, the device models must be selected separately for the data write and data read modes.
• Number of random pulses for eye diagram: Means the number of random pulses excited to the simulating net during the eye diagram analysis.
• DDR Spec: The setup time of input signal is automatically filled if user use Import DDR Spec. You can modify each parameter.
• Bit pattern style: Select the numerical method among random, ABS (Artificial Bit Stream) and PRBS (Pseudo Random Bit Stream) for generating the bit sequences. ABS (Artificial Bit Stream) is a method designed to provide a large pattern of bits to show worst case signal transmission quality of the net that would quickly converge the eye diagram. PRBS (Pseudo Random Bit Stream) is the mostly common method deemed as an industry standard.
• Bit pattern length: If bit pattern style is ABS or PRBS, choose the bit pattern length here.
• Preamble time(pS): Enter this value. Simulation start after this time to wait until status of internal circuit becomes stable.
• DQS jitter(pS): Enter system DDR bus DQS jitter value.
• Clock jitter(pS): Enter system DDR bus clock jitter value.
• ADD/CMD/CTRL signal mode: Select DDR ADD/CMD/CTRL timing mode.
  • 1T: The frequency of ADD/CMD/CTRL signals are half of the frequency of clock signal.
  • 2T: The frequency of ADD/CMD/CTRL signals are 1/4 of the frequency of clock signal.
• Simulation Mode: Users can select the simulation type also among Typical, Fast, and Slow. The simulation type is applied to all device models used for the analysis.
• Import DDR Spec: In order to analyze DDR timing, user has to enter every timing parameter manually. But upon clicking Import DDR Spec button, users can automatically bring in a DDR timing specification to use among available DDR timing tables. Depeding on the Read/Write Cycle, different DDR specs can be used.

  
  
  

• DDR Spec Generator: Users can also generate a new DDR timing specification into the exist DDR timing tables.
• Vref_DQ Setting: Normally the voltage level of Vref_DQ for timing check is defined by specification. But some technology memories, such as DDR4, require setting Vref_DQ value by user. Using this option, you can assign Vref_DQ voltage level.
• Extract Vref_DQ using analysis result: Using this option, the DFE+ tool find the appropriate Vref_DQ value during analysis.
• Vref_DQ training result: User can assign Vref_DQ value for each memory component manually.