Approach Pair Comp

There are occasions that components should be connected to certain signals and placed together with other components.
  • A transient load decoupling capacitor should be placed as close as possible to the device requiring the decoupled signal. The goal is to minimize the amount of line inductance and series resistance between the decoupling capacitor and the intended device.
  • A power supply decoupling bypass capacitor should be placed as close to the voltage/current source as possible. The idea is to minimize the line inductance and series resistance between the capacitor and the supplied devices.
  • Placing a ferrite-bead close to the noise generating component pin helps reduce EMI. The Approach Pair Component rule checks for a pair status of components.
  • Item: Enter item name.
  • Comp1: Select the 1st target pair component group.
  • Comp2: Select the 2nd target pair component group.
  • Distance: Assign distance criteria to the two components.
  • Net: Select a net group to be connected to pin.
  • Measure Base: Select measure point.
    • Pin Shape: Measure pin edge to edge.
    • Pin Location: Measure pin center to center.
    • COC: Measure COC to COC in case of component distance check.
    • Silk: Measure Silk to Silk in case of component distance check.
  • Layer: Select a layer on which second components should be placed.

    • Same Layer: Check same layer only.
    • Opposite Layer: Check TOP/BOT layer only.
    • Any Layer: Check all layer.
  • Nearest Comp: If the selected component is multiple, upon selecting, check nearest component only.
  • Pair Comp: Upon selecting this option, if the distance condition meets the requirement, DFE excludes that component for further testing.
  • Remove No Comp to Check: DFE will not report No Comp To Check error.


Layout of Decoupling
Besides the capacitive effect of the ground plane under the microcontroller, the fast current has to be delivered from the discrete decoupling capacitors.

Decide for pin-decoupling and/or global decoupling.

Sketch of layout
By pin-decoupling each pair of VDD-GND pads is first contacted to the capacitor(s) and then to the supply layers/nets.
  • Advantage: Optimized decoupling for every pin possible.
  • Disadvantage: High number of capacitors required.

Place capacitor-pad as close as possible to the microcontroller’s VDD/GND pins.

First contact the capacitor, and then contact the vias to GND and VDD plane.

The connection from the decoupling capacitor to the ground plane can also be realized by several microvias inside the outline of the capacitor pad. That guarantees a low impendent and low inductive connection to ground.

If possible, keep the decoupling capacitor on the same side as the MC. Remember vias as additional inductance.

Design traces between pads and capacitor as wide as possible.

If you need to place the capacitors on the bottom side of the board provide two or more vias in parallel. Think about using micro vias if possible.

Keep GND-vias and VDD-vias as close together as possible.