ADD/CMD/CTRL Line Analysis Dialog Parameters

The Analysis > Signal Integrity > ADD/CMD/CTRL Line Analysis menu enables you to analyze address/command/control group nets of DDR BUS in a one operation step.
Figure 1.


  1. Select Clock signal nets: Clock signal net for analysis can be selected over Select Net dialog.
  2. Select Address/Command/Control signal nets: Address/Command/Control nets for analysis can be selected over Select Net dialog.
  3. Net Name: All selected net names will be listed.
  4. Active Driver: You can specify the active driver pin among the connected pin to this net. The other pins will be assigned as receiver pin(s) automatically. Only CPU component can be selected as an active driver pin.
  5. Device Models: For the selected active driver, actual driver model can be selectable among many different models in IBIS or Linear device model types. You can use one of available models considering the output impedance, driving capability measured by output current level and operating frequencies. These driver’s characteristics lead huge impact on the simulated waveforms.
    Figure 2.


  6. Number of random pulses for eye diagram: Means the number of random pulses excited to the simulating net during the eye diagram analysis.
  7. Bit pattern style: Select the numerical method among random, ABS (Artificial Bit Stream) and PRBS (Pseudo Random Bit Stream) for generating the bit sequences. ABS (Artificial Bit Stream) is a method designed to provide a large pattern of bits to show worst case signal transmission quality of the net that would quickly converge the eye diagram. PRBS (Pseudo Random Bit Stream) is the mostly common method deemed as an industry standard.
  8. Bit pattern length: Ff bit pattern style is ABS or PRBS, choose the bit pattern length.
  9. Preamble time: Simulation start after this time to wait until status of internal circuit becomes stable.
  10. Clock Speed (Mbps): Shows DDR BUS operating speed.
  11. Setup time: Shows required setup time.
  12. Hold time: Shows required hold time.
  13. DC threshold: Shows threshold voltage value for hold time measurement.
  14. AC threshold: Shows threshold voltage value for setup time measurement.
  15. Clock Jitter (PS): Enter system DDR address bus jitter value.
    1. Import: By clicking Import tab users can choose required DDR operating speed from pre-defined table. Then the contents field is filled with pre-defined value from JEDEC specification.
    2. Run Analysis: Simulation starts.
    3. Show report: The analysis results can be listed in a table form by clicking Show Report tab. They can be also shown in MS Excel.
    4. Save: Saves the file in Signal_Integrity/Waveform directory under the PCB design job folder. The model name plus .spe is used for the file name. The saved eye diagram waveform data can be read into the waveform viewer alone or together with other eye diagram waveform data.
    5. Model Name: Model name of the simulated and saved nets are listed.
    6. Copy: Enables the selected net(s) to be registered at Select Net region for analysis.
    7. ADD/CMD/CTRL signal mode: Select address bus mode.