In addition to wave propagation delays along the interconnections, the transmitted
signals are distorted by reflection noises. Reflection noise is the excessive
voltage caused at the driving and receiving ends of an interconnection during signal
switching. It strongly depends on the characteristic impedance of the line and the
impedance of the driving and receiving circuitry. Reflection noise is also produced
when the interconnect cross-section undergoes changes along the signal propagation
path.
Multiple nets can be selected for
analysis, but each net is modeled separately without coupling it to other nets. When
a differential net is selected the other differential pair, net is also
automatically selected, and both differential pair nets are included in the same
network analysis model.
Figure 1.
Creating a network analysis model starts with selecting a net from the net listing.
The net name is initially assigned to the model name which can be changed by users.
When multiple output or bi-directional pins are available for the net, one of them
must be selected for active driver pin. The pulse period of input signal is
automatically obtained from the operating frequency of the net. Clicking
Input Signal allows you to view the input signal property
and change them. After checking Define Pulse Data, you can also change the high/low
state of each bit of the input signal.
Figure 2.
Clicking Device Models allows you to view the device models
selected for the output and input pins. Users can change the device model selection
when multiple models are available for the pin.
Figure 3.
Prior to running analysis, you need to select an analysis type and make necessary
changes on the analysis control parameters. Available analysis types are:
Waveform
Eye Diagram
Network Parameter
TDR
Analysis run control parameters vary with the analysis type and are initialized
with the ones shown in Electrical Analysis Constraints menu.
Waveform Analysis
Waveform analysis is running transient circuit simulation on the network model for
user-specified simulation time to obtain time-domain voltage waveforms at the input
and output nodes. Signaling time refers how long the driver pin keeps transmitting
signals. To see the waveforms after the driver pin becomes inactive, the simulation
time should be longer than the signaling time plus the signal delay of the input
signal.
The analysis is performed upon selecting Analyze menu. Upon
completion of the analysis, waveforms at all input and output nodes are displayed.
For each output pin, you can view:
measurement voltage (Vmeas)
input signal (*_in)
enable signal (*-en)
For each input pin, you can view:
static overshoot voltage high (Vmax)
static overshoot voltage low (Vmin)
logic threshold voltage high (Vinh)
logic threshold voltage low (Vinl)
Selecting or unselecting an input node for waveform display
makes the differential pair node be automatically selected or unselected. Many
displays and measuring options are available in the waveform viewer. The analysis
results can be listed in a table form by clicking the Result
Data tab. They can be also shown in MS Excel. The waveform data can
be saved in a file with the use of Save or Save As menu. Save menu saves the file in
Signal_Integrity/Waveform directory under the PCB design
job folder. The model name plus .spw is used for the file name.
The saved waveform data can be read into the waveform viewer alone or together with
other waveform data for a review or comparison.
Figure 4.
Eye Diagram Analysis
Eye Diagram analysis is running transient circuit simulation on the network model to
obtain eye diagrams at the input nodes. An eye diagram or eye pattern is obtained
from overlapping multiple waveforms at the receiver node of a net generated by
randomly selected high/low states of the input signals for the selected net and
adjacent nets. The coupling effects from the adjacent nets are reflected in the
waveforms. Prior to running analysis, users can change the analysis control
parameters such as the number of random pulses and bit pattern style.
Upon completion of the analysis, the eye diagrams at input nodes are displayed in the
waveform viewer. Check Eye menu allows users to check if the eye size is large
enough with the use of eye mask. The height and width values of the eye mask are
initialized with the ones defined for the net, and users can change them. Among many
available display and measurement options, Box can be effectively used for measuring
the eye size. With X box checked users can make a rectangular box by placing two
vertical lines. The eye mask height is used for the box height. On the other hand,
with Y box checked users can make a rectangular box by placing two horizontal lines.
The eye mask width is used for the box width. The eye diagram waveform data can be
saved in a file with the use of Save or Save As menu. Save menu saves the file in
the Signal_Integrity/Waveform directory under the PCB design
job folder. The model name plus .spe is used for the file name.
The saved eye diagram waveform data can be read into the waveform viewer alone or
together with other eye diagram waveform data.
Figure 5.
Network Parameter Analysis
Network Parameter analysis is running AC circuit simulation on the interconnect
network model to obtain network parameters between the ports in the model. A port is
assigned to each pin location. The analysis results for each frequency point include:
scattering (S)
admittance (Y)
impedance (Z)
parameter matrices
Prior to running analysis, you can change the analysis control parameters such
as the starting and ending frequency points, frequency sweep type, and number of
frequency points for the sweep type.
Upon completion of the analysis, the S-parameter magnitude values among ports are
initially displayed in the network parameter viewer. You can change the port pair
selections and change the value type to decibel, phase, real number, or imaginary
number. You can choose the network parameter type for the display among S-parameter,
Y-parameter, and Z-parameter. Many display and measurement options are available in
the network parameter viewer. Result Data menu is used to list the network parameter
values in a table format. The network parameter values can be saved in a Touchstone
format file. Additionally, they can be viewed in MS Excel.
Figure 6.
TDR Analysis
TDR analysis is running transient circuit simulation on the network model to obtain
reflected waveform to generate the impedance waveform (TDR) seen from the driver.
TDR analysis only considers the wave reflected to the driver stage. Multiple
reflection is not considered.
Figure 7. You can select multiple network analysis models for analysis. The selected
models are analyzed one by one, and the analysis results are displayed together. The
network models with analysis results are saved in
Signal_Integrity/NWK directory under the PCB design job
folder by selecting Save menu. The model name plus .NWK is used
for the file name. The saved models are listed in the left-hand side of the dialog.
You can select the saved models anytime and copy the model to view the model, view
the analysis results, edit the model, and rerun analysis.
Outputs
The Analysis > Signal Integrity > Network Analysis menu enables user to execute three
different types of analysis mentioned above. The output waveform is influenced by
the signal delay and reflections of the selected net(s) but not by the crosstalk
from the neighboring nets.
Waveform Analysis: EM simulation will give SPICE netlist for the selected
net and Spice source will be applied to it to do the transient
analysis.
Time domain voltage waveforms for the driver/receiver pins connected to the
selected net will be displayed automatically after the SPICE analysis
done.
Eye Diagram: Random bits sequence will be applied to the selected net(s) and
the eye diagram which shows the quality of the transmitted signals (bits)
passing through it will be displayed repeatedly over the specified Pulse
Period.
Network Parameter: Extracts S, Y and Z parameters for the selected traces.
Using Network Parameter Viewer, user can investigate the parameters in both
graphic and table data format. S parameter can be exported as touch stone
file. It can extract N-ports (of S, Z, and Y parameters) into the industry
standard, Touchstone format, which can be used for subsequent analysis of
larger scale systems.
Touchstone Data Format are extracted to MA(magnitude), DB(decibel), and
RI(real & imaginary number).
Figure 8.
TDR Analysis: TDR analysis is running transient circuit simulation on the
network model to obtain reflected waveform to generate the impedance
waveform (TDR) seen from the driver. TDR analysis only considers the wave
reflected to the driver stage. Multiple reflection is not considered.
