Signal integrity (SI) is a measure of the quality of an electrical signal.

In digital electronics, a stream of binary values is represented by a voltage or current waveform. Over short distances and at low bit rates, a simple conductor can transmit this width sufficient fidelity. However, at high bit rates and over longer distances, various effects can degrade the electrical signal to the point where errors occur, and the system or device fails. The purpose of signal integrity tool is to analyze and mitigate these impairments.

Signal Integrity Analysis menus allow you to validate the design decisions throughout the design process including the selection of parts, materials, and board layer stack-up and create the net topology. At a pre-route stage, it can be effectively used with various topology options to find routing constraints for critical nets. To easily build up the practical complex topologies, this feature allows you to study versatile net topologies depending on signaling types. For example, Single-ended, Differential, and Multi-coupled using built-in topology model libraries.

Simulation of PCB design after placement and routing is good, but simulation beforehand is better. The PollEx SI Explorer allows you to perform pre-layout simulation. The main purpose of pre-layout simulation is to develop design constraints, while post-layout simulation’s main goal is to verify compliance with those constraints. Pre-layout analysis allows a designer to identify and eliminate signal integrity, crosstalk, and EMI issues early in the design process. This is the most cost-effective way to design a board with fewer iterations.

Figure 1.

Major Capabilities

  • Topology editor provides flexible and convenient ways to develop net routing topologies for certain critical nets. For example, high-speed clock and small analog signal as of in type of single-ended, differential, multi-coupled and system-level.
  • Extract frequency dependent network parameters (S, Y, Z) and parasitic SPICE models in the forms of capacitance, inductance, resistance, and conductance for PCB interconnects configured with strip/micro-strip lines and vias.
  • Transmission Line Analysis enables optimal physical dimensions of PCB interconnects (single-ended, differential pair) with designated stack up condition having desired electrical characteristics. For example, characteristic impedance, R, L, C, G, delay/unit length, velocity, attenuation, skin depth, and so on.
  • Signaling waveforms travelling among IC driver and receivers of the selected nets can be automatically displayed, which reflects the effect of net topology, driver’s DC/AC characteristics, bias, and termination strategies. Signal delay, inductive/capacitive coupling, and reflection phenomena are accounted for getting the travelling waveforms.
  • Eye-diagram representing the quality of signal transmission can be extracted depending on the bit (pulse) shape and big generating algorithms (Random, ABS and PRBS).