SI Explorer Tutorial

Build PCB Stack

  1. From the menu bar, click Options > SI Explorer.
    The SI Explorer dialog opens.
  2. From the menu bar, click File > New.
    The New Design dialog opens.
  3. Enter a new design name and select a folder in which the new design folder is created.
    Figure 1.


  4. Click OK.
    The SI Explorer dialog opens.
  5. From the menu bar in the SI Explorer dialog, click Property > Layers.
    The Layer Stacks dialog opens.
  6. Click Import.
    The Explorer dialog opens.
  7. Navigate to the location of the default stack-up files.
    The directory location of your own stack-up files: C:\ProgramData\altair\PollEx\<version>\Examples\Solver\SI\Stackup.
  8. Select the L6_Type1.udls file and click Open.
  9. Click Open to close the Explorer dialog.
    Our stack-up should now look as shown in .
    Figure 2.


  10. Click OK to close the Layer Stacks dialog.

Add New Dielectric Material

In this step, you will add new dielectric material FR4.0.

  1. From the menu bar, click Property > Materials.
    The Materials dialog opens.
  2. Click Add Dielectric.
    The Edit dialog opens.
  3. For Material name, enter FR4.0.
  4. For the Z, Y, and Z fields, enter 0.35.
  5. For Dielectric Constant, enter 4.0.
  6. For Loss Tangent, enter 0.02.
    Figure 3.


  7. Click OK to close to close Edit dialog.
    The FR4.0 material is registered as a new material named FR4.0.
    Figure 4.


  8. Click OK to close to close Materials dialog.

Create Arbitrary Part

In this step, you will create an arbitrary part and assign an IBIS model.

  1. From the menu bar in the SI Explorer dialog, click Properties > Parts.
    The Parts dialog opens.
  2. Click Create Part.
    The Create Part dialog opens.
  3. For Part name, enter CPU.
  4. For Pin count, enter 513.
    Figure 5.


  5. Click OK.
    The Electrical & Thermal Properties dialog opens.
  6. Click Device Model Files.
    The Device Model Files dialog opens.
  7. Click Add.
    The Model File dialog opens.
  8. For Model type, select IBIS.
    Figure 6.


  9. Click .
    The Explorer dialog opens.
  10. Navigate to the IBIS model directory and select the CPU.ibs file from C:\ProgramData\altair\PollEx\<version>\Examples\Solver\SI\Simulation_Model.
  11. Click Open.
  12. Click OK to close the Model File dialog.
  13. In the Device Model Files dialog, click Display.
    Figure 7.


    The IBIS Manager dialog opens.
  14. In the Model tab, select DDR3_240ohm.
  15. Review the AC/DC properties.
    By exploring the buffer’s AC/DC characteristics, you can choose the proper buffer model for SI Analysis.
    Figure 8.


  16. Click Close to close the IBIS Manager panel.
  17. Click OK to close the Device Model Files panel.
    Figure 9.


  18. In the Select Component dialog, select CPU1 and click OK.
  19. Click OK to close the Electrical & Thermal Properties dialog.
    The controller is registered in the Parts dialog.
    Figure 10.


  20. Click Close to close the Parts panel.

Create Arbitrary Passive Part

In this step, you will create an arbitrary passive part and assign RLC model.

  1. From the menu bar, click Properties > Parts.
    The Parts dialog opens.
  2. Click Create Part.
    The Create Part dialog opens.
  3. For Part name, enter Resistor.
  4. For Pin count, enter 2.
    Figure 11.


  5. Click OK.
    The Electrical & Thermal Properties dialog opens.
  6. Click Passive Component Data.
    The Passive Component Data dialog opens.
    Figure 12.


  7. For Nominal Value, enter 33ohm.
  8. For Resistance (Ohm), enter 33.
  9. Click OK to close the Passive Component Data dialog.
  10. Click OK to close the Electrical & Thermal Properties dialog.
    The resistor is registered in the Parts panel.
    Figure 13.


  11. Click Close.

Assign Passive Component Data

  1. From the menu bar, click Properties > Parts.
    The Parts dialog opens.
  2. Click Create Part.
    The Create Part dialog opens.
  3. For Par name, enter R_Network.
  4. For Pin count, enter 8.
    Figure 14.


  5. Click OK.
    The Electrical & Thermal Properties dialog opens.
  6. Click Passive Component Data.
    The Passive Component Data dialog opens.
  7. For Nominal Value, enter 10ohm.
  8. For Resistance (Ohm), enter 10.
    When a passive is an array component, you must define the pin pair configuration.
    Figure 15.


    Figure 16.


  9. Click Pin Pairing.
    The Pin Paring dialog opens.
  10. Click Add.
    The Pin Select dialog opens.
  11. Select pin name 1 and 8 as the first pin pair.
  12. Click OK.
  13. Repeat steps 10 - 12 to define the remaining three pin pairs.
    The specified passive component values will be assigned separately to these paired pins.
    Figure 17.


  14. Click OK to close the Pin Paring panel.
  15. Click OK to close the Passive Component Data dialog.
  16. Click OK to close the Electrical & Thermal Properties dialog.
    The resistor is registered in the Parts dialog.
    Figure 18.


  17. Click Close to close the Parts dialog.

Create Part Using IBIS Model

  1. From the menu bar, click Properties > Parts.
    The Parts dialog opens.
  2. Click Create Part from IBIS.
    The Explorer dialog opens.
  3. Open the Memory.ibs file.
    The Electrical & Thermal Properties dialog opens.
  4. Click OK to close the Electrical & Thermal Properties dialog.
    Figure 19.


    The new part is created.
    Figure 20.


  5. Click Close to close the Parts panel.

Import Parts from Previous Design PDBB

  1. From the menu bar, click Properties > Parts.
    The Parts dialog opens.
  2. Click Import.
    The Explorer dialog opens.
  3. Navigate to the UPF directory: C:\ProgramData\altair\PollEx\<version>\Examples\UPFs.
  4. Click OK to import the UPF directory contents.
    The Parts dialog opens. Every part in the upfs/Parts directory is imported.
    Figure 21.


  5. Click Close in the Parts dialog.
  6. From the menu bar, click File > Save to save this design.
  7. From the menu bar, click File > Close to close this design.

Import PDBB Design File

  1. In the SI Explorer dialog, click File > New.
    The New Design dialog opens.
  2. Enter a new design name and select a folder in which the new design folder will be created.
    Figure 22.


  3. Click OK to create new design project.
  4. In the SI Explorer dialog, click File > Import from thePollEx PCB.
    The Explorer dialog opens.
  5. Select the PollEx_New_Sample.pdbb file and click Open.
    The imported transmission line models, Via Models, and net topology models are listed in the SI Explorer dialog.
    Figure 23.


    After importing, you must assign a simulation model. Here, you will use the import method from the unified part library.
  6. In the SI Explorer dialog, click Properties > Part.
    The Part dialog opens.
  7. Click Import.
    The Explorer dialog opens.
  8. Navigate to the UPF directory and click OK to import UPF directory contents.
  9. Close the Part dialog.

Extract Transmission Line Properties

  1. In the SI Explorer dialog, click Analysis > Transmission Line Analysis.
    The Transmission Line Analysis dialog opens.
  2. For Model name, enter CLOCK.
    Figure 24.


  3. Select Extract Trace Parasitic Parameters.
  4. Click Add Conductor.
    The Conductor Information dialog opens.
  5. For Width, enter 0.1.
    Figure 25.


  6. Click OK.
    The created transmission line model is displayed in the model field.
  7. Click Display Model at the bottom of the Transmission Line Analysis dialog.
    Figure 26.


    The CLOCK dialog opens.
  8. Verify the stack up and trace shape and click Close.
    Figure 27.


  9. Click Analyze.
    The Transmission Line Analysis-Display Results dialog opens. The default properties shown on the right side are Char-Impedance. You can switch the property display by clicking other characteristic.
    Figure 28.


  10. Click Close.
  11. Click Save.
    The CLOCK model is registered in the Model Name window.
    Figure 29.


  12. Click Add Conductor.
    The Conductor Information dialog opens.
  13. For Width (mm), enter 0.1.
  14. For X (mm), enter 0.2.
  15. Click OK.
    X represents the distance between the centers of two traces.
    Figure 30.


  16. In the Transmission Line Analysis-Display Results dialog, click Display Model.
  17. Verify the stack up and trace shape and click Close.
    Two traces will be located at the same signal layer numbered as 1.
  18. Click Analyze.
    The Transmission Line Analysis-Display Results dialog opens. The analyzed properties shown at right side are Diff-Impedance.
  19. Click characteristics to switch the property display.
  20. Click Close.
    Figure 31.


Get Impedance Matching Trace

  1. In the Transmission Line Analysis dialog, enter CLOCK_Diff for the Model name.
  2. Select Get Impedance Matching Trace.
  3. For Signal type, select Differential narrow.
  4. For Unknown property, select Separation.
  5. For Trace width (mm), enter 0.1.
  6. For Differential impedance (ohm), enter 100.
  7. Click Analyze.
    Figure 32.


  8. In the Transmission Line Analysis-Display Results dialog, check the calculated Diff-Impedance value.
  9. Click Close.
    Figure 33.


  10. Click Save.
    Figure 34.


  11. Click Close to close the Transmission Line Analysis dialog.

Analyze Single-Ended Topology

  1. In the SI Explorer dialog, click Analysis > Net Topology Analysis.
    The Net Topology Analyzer dialog opens.
  2. From the Net Topology Analyzer dialog, click File > New.
    The Net Model Name dialog opens.
    Figure 35.


  3. Model Name, enter Clock.
  4. For Net Type, select Single-ended.
  5. Click OK.
    The Single-ended dialog opens.
  6. Select Typ5 which has parallel ac termination and click Close.
    Figure 36.


    The Net Topology Analyzer dialog opens.
  7. Select R2, C2, C1, and GND.
  8. Press Delete.
    All four elements below are removed.
    Figure 37.


  9. Click VCC.
  10. For Voltage (V), enter 0.75, and click Apply.
    Figure 38.


  11. Click U1-1 and click .
    Figure 39.


    The Select Part/Pin dialog opens.
  12. Enable the NXP4330 and L2 checkboxes.
    Figure 40.


  13. Click OK.
  14. In the Net Topology Analyzer dialog, click the single line model.
    Figure 41.


  15. For Model Name, select CLOCK.
  16. For Length (mm), enter 10.
  17. Click Apply.
    Figure 42.


  18. Click R1.
  19. For Resistance, enter 50.
  20. Click Apply.
    Figure 43.


  21. Click U2-1 and click .
    The Select Part/Pin dialog opens.
  22. Enable the H5TQ4G63AFR and J7 checkboxes.
  23. Click OK.
    Figure 44.


  24. Click Analysis > Network Analysis.
    The Topology Network Analysis dialog opens.
  25. Click Analyze.
    The Waveform Viewer dialog opens and displays the simulated waveform.
    Figure 45.


  26. Click Close.
  27. From the menu bar, click File > Save As to save this topology.
  28. Save this topology as Clock.ntfb.
  29. Close the Net Topology Analyzer dialog.

Explore Waveform Analysis

  1. In the SI Explorer dialog, click Analysis > Net Topology Analysis.
    The Net Topology Analyzer dialog opens.
  2. Click .
    The Net Model Name dialog opens.
    Figure 46.


  3. For Model Name, enter DDR_Data.
  4. For Net Type, select Single-ended.
  5. Click OK.
    The Single-ended dialog opens.
  6. Select Type1 and click Close.
    Figure 47.


    The Net Topology Analyzer dialog opens.
  7. Click U1-1 and click .
    Figure 48.


  8. Enable the H5TQ4G63AFR and A2 checkboxes.
    Figure 49.


  9. Click OK.
  10. Click U2-1 and click .
    Figure 50.


  11. Enable the IC-NXP4330 and F5 checkboxes.
    By assigning this pin model, the Receiver will be terminated with 120ohm resistor described in IBIS file.
    Figure 51.


  12. Click single line model and select CLOCK as the Model Name.
    The selected trace model denotes that it is routed at 1 layer with 0.1 (mm) width. The thickness of the trace and distance to the ground will follow the stack up information.
  13. Enter 10 as the length.
  14. Click Apply.
    Figure 52.


  15. From the menu bar, click File > Save As.
  16. Save this topology as DDR_Data.ntfb.
  17. From the menu bar, click Analysis > Network Analysis.
    The Topology Network Analysis dialog opens.
    Figure 53.


  18. In the Active Driver Pin field, click and select U1_A2.
    Device pin model => U1_A2. U2_F5 is the reference pin name of a receiving device.
  19. Change the Pulse Period to 1.25 and click Input Signal.

    Total Pulse Period: (1.25) ns = TR (0.01) + 2 * PW (0.615) + TF (0.01).

    TD will not change any among Initial State ~ Input Signal, means it just add specified time as latency of the excitation. 1.25ns pulse will be applied just after the TD(ns) pauses.

    Figure 54.


  20. Enable Define Pulse Data checkbox to specify the switching format.
    Figure 55.


  21. Click OK to close the Input Signal dialog.
  22. In the Topology Network Analysis dialog, click Device Models in the Device Models field.
  23. For U1, select DQ_DRV_34 for model.
  24. For U2, select ODT_120 for model and click OK.
    Figure 56.


    The waveform analysis is ready.
  25. Click Analyze at the bottom of the Topology Network Analysis dialog.
    When the waveform analysis is started, electromagnetic simulation will extract the SPICE model for the selected net. The excitation source signal will be applied to the net which is specified by the assigned pin model’s operating characteristics and the values defined at Input Signal and Pulse Period. When the simulation is done, the Waveform Viewer dialog will be displayed as above for exploring the waveforms.
    Figure 57.


  26. Click Close.

Explore Eye Diagram Analysis

  1. In the Topology Network Analysis dialog, select Eye Diagram for Analysis Type.
  2. Click Input Signal.
    The Input Signal dialog opens.
  3. Disable the Define Pulse Data checkbox and click OK.
    Figure 58.


  4. Select PRBS for Bit Pattern style.
  5. Select 2^7 for Bit pattern length.
    All 2^7 numbers of random bit will be applied to the net; the detailed bit signal pattern will follow the shape defined at Input Signal.
    Figure 59.


  6. Click Analyze.
    The waveform analysis starts. When the simulation is done, the Waveform Viewer dialog opens.
  7. In the Waveform Viewer dialog, enable the U2_F5 checkbox.
  8. Click View Option.
    The View Option dialog opens.
  9. Change the value of the Eye Mask region as shown below and click Check Eye.
  10. Eye mask will come up then move the cursor and click near the center of the eye pattern.
    Figure 60.


  11. Click Close.

Explore Network Parameter Analysis

  1. In the Topology Network Analysis dialog, select Network Parameter for Analysis Type.
    This enables the S, Y, Z-Parameter extraction to the selected net(s). 300 frequency points will be taken for the parameter extraction.
    Figure 61.


  2. Click Analyze.
    The Network Parameter Viewer dialog opens.
  3. Click Result Data to verify the extracted parameters in table data format.
    Figure 62.


  4. Select Port U1_A2::U2_F5.
  5. Select MA as a Touchstone Data Format.
  6. Click Export to Touchstone File to extract S-Parameters in Touchstone file format.
    Figure 63.


    The Explorer dialog opens.
  7. Click Save to save this S-Parameter files.