LogicalDelay

Delay boolean signal

    LogicalDelay

Library

Modelica/Blocks/Logical

Description

When input u gets true, output y1 gets immediately true, whereas output y2 gets true after delayTime.

When input u gets false, output y1 gets false after delayTime, whereas output y2 gets immediately false.

Parameters

LogicalDelay_0

NameLabelDescriptionData TypeValid Values

mo_delayTime

delayTime

Time delay

Scalar

LogicalDelay_1

NameLabelDescriptionData TypeValid Values

mo__nmodifiers

Number of Modifiers

Specifies the number of modifiers

Number

mo__modifiers

Modifiers

Add new modifier

Structure

mo__modifiers/varname

Variable name

Cell of strings

'tSwitch'

mo__modifiers/attribute

Attribute

Cell of strings

'start'
'fixed'

mo__modifiers/value

Value

Ports

NameTypeDescriptionIO TypeNumber

u

implicit

input

1

y1

implicit

output

1

y2

implicit

output

2

See Also