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PollEx User Guides
Discover PollEx functionality with comprehensive user guides.
Solver User Guides
This section contains the user guides for the following tools: PI, SI, SI Explorer, and Thermal.
SI Explorer
Analysis
In this section, you can learn how to do pre-layout SI Analysis.
Net Topology Analysis
Net topology analysis is used to construct or view the detailed physical topology of nets schematically and run signal integrity analysis on the interconnect network model.

Welcome
What's New
View new features for PollEx 2024.1.
Get Started
Learn the basics and discover the workspace.
PollEx Tutorials
Discover PollEx functionality with interactive tutorials.
PollEx User Guides
Discover PollEx functionality with comprehensive user guides.
- Manufacture User Guides
  This section contains the user guides for the following tools: Block JIG Generator, Compare GDSII, Gerber to PCB, Make Board Paneling, Metal Mask Manager, Mounting Data Extractor, Mounting Emulator, Router-Machine JIG Generator, Solder Quantity Calculator, Soldering Pallet, Test Point Location Generator, and Underfill.
- Modeler User Guides
  This section contains the user guides for the following tools: BOM, CAM, Component Arrangement Plan, CP, Golden Sample, Logic, PCB, Redmark+, and Worksheet Planner.
- Solver User Guides
  This section contains the user guides for the following tools: PI, SI, SI Explorer, and Thermal.
  - PI
  - SI
  - SI Explorer
    - Introduction
      Signal integrity (SI) is a measure of the quality of an electrical signal.
    - Setup Methods
      The PollEx SI Explorer is a pre-layout simulation tool. It can be used for experimenting with various topology options to find routing constraints for critical nets.
    - Start from Scratch
      For easy building up the practical complex topologies, this feature allows you to study versatile net topologies depending on signaling types, for example: Single-ended, Differential, and Multi-coupled using built-in topology model libraries.
    - Setup Via Padstacks
      Manage via padstacks for electrical analysis.
    - Use Previous Design File
      You can use previous design file environment if you have previous design .pdbb file.
    - Analysis
      In this section, you can learn how to do pre-layout SI Analysis.
      - Edit Electrical Analysis Constraints
        View editable versatile control parameters which influence the simulation/analysis results for network, electromagnetic field, eye-diagram, and SPICE.
      - Transmission Line Analysis
      - Net Topology Analysis
        Net topology analysis is used to construct or view the detailed physical topology of nets schematically and run signal integrity analysis on the interconnect network model.
        Basic Menu Functions
        Functions available in the net topology analyzer menus.
        Compose Net Topology
        Study versatile net topologies depending on signaling types, such as Single-ended, Differential, and Multi-coupled using built-in topology model libraries.
        Supported Elements
        Supported elements for topology composition.
        Built-in Topologies
        Analyze Net Topology
        After finishing net topology construction and assigning a simulation model, analyze net topology using the Net Topology Analyzer.
      - Waveform Viewer
        Open files containing transient analysis waveforms or eye diagrams and review the waveforms.
  - Thermal
- Verification User Guides
  This section contains the user guides for the following tools: DFA, DFE, DFE+, DFM, and Logic DFE.
- UPE User Guides
  This section contains the PollEx UPE user guide.
PollEx Installation Guide
Instruction to install PollEx 2024.1.
Character String Search Rule
Definition for meta character using in making sentence for searching option.

Net Topology Analysis

Net topology analysis is used to construct or view the detailed physical topology of nets schematically and run signal integrity analysis on the interconnect network model.

At a pre-route stage, it can be effectively used for playing with various topology options to find routing constraints for critical nets.

By using Net Topology Analyzer, PCB designer or SI engineer can draw optimized signaling topology for the specific or critical nets which operate with very small signal or at very high speed. Routing topology and termination method should be carefully decided for the analog and high-speed digital signal like as clock to guarantee the proper transmission of the signals. Depending on the number of loading ICs and routing length, using termination couldn’t avoidable. Driver’s AC/DC characteristics also one of key factor affects the signaling quality for the PCB system then all what if SI analysis should consider this.

When you select the menu Analysis > Net Topology Analysis Net Topology Analyzer dialog will display.