Verify Netlist
Use Verify Netlist to compare PCB design and net list files that are used in the manufacturing process (*.fpn and *.net).
From the menu bar of Test-Point Location Generator,
click .
- FPN Path: The FPN file is exported from the Bare Board Tester (BBT) with the pin number and the pin name.
- Net Path: The NET file is exported from the BBT with the net name and the pin number.
Verified results display according to the Setting for Verification settings.Figure 1.
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The terms used in the Verification Result are as follows:
Term | Description |
---|---|
PCB | Net name in PCB design. |
JIG | Net name in imported netlists. |
ALL | Number of extracted JIG (Test Point) data. |
PCB | Number of connected pins in PCB design. |
JIG | Number of connected pins in imported netlists. |
D-PCB | Number of connected pins only in PCB design excluding the connected pins in the net on both PCB design and netlists. |
D-JIG | Number of connected pins only in netlist, excluding the connected pins in the net on both PCB design and netlists. |