This tutorial uses a special mapping with inherited connectivity for the power and ground stubs.
As an example, we use the Spice file demo/spice/inv.sp.
Please make sure that you have installed a license file which contains - in addition to one of the master GUI features - the feature gv-skillexport.
For an overview of the used concepts see the Skill Export tutorial.
FIRST STEP - Use Mapping To an Inherit Symbol
After generating the symbol mapping template with the help of the cadence2symlib.il script in Cadence Virtuoso activate the desired mapping by removing the comment character # at the needed lines.
In analogLib.sym we enable the mos mapping and in contrast to the Skill Export tutorial we use the vdd_inherit and vss_inherit symbols for the inherit power/ground mappings.
spice nmos4 analogLib MN * spice pmos4 analogLib MP * symio vss_inherit pg0 * * analogLib vss symio vdd_inherit pg+ * * analogLib vdd
The interface ports are mapped with the symio lines in the basic.sym file.
symio ipin in * * basic symio opin out * * basic
A detailed description of the syntax of these lines can be found in the reference manual.
SECOND STEP - Load Design
As described in the Skill Export tutorial enable the visibility of all bulk pins, open the Read Spice dialog, add the mappings for basic.sym and analogLib.sym, and export the inv.il Skill file.
THIRD STEP - Load Skill into Cadence
Load the Skill file you have created in the previous step, using the following input line of the Command Interpreter Window (CIW):
load("inv.il")
Use , select the library sv_lib, the cell INV and the view "schematic".
FOURTH STEP - Add Top Level
If there is no existing symbol it can be created using .
In the Cadence environment add a top level schematic and instantiate the created inverter.
To set the specific power/ground nets for the inverter schematic below, add properties for "vdd" (here "3V") and "vss" (here "my_gnd") with type netSet.
FIFTH STEP - Create Netlist
As described in the Skill Export tutorial, the netlist can be created to verify the correct inherited connections.
