This tutorial demonstrates the usage of the command line tools.
For more information, please consult to the Command Line Arguments documentation for each tool in the doc/parser
directory.
Overview
The use of the command line tools allows many combinations of different input descriptions for library cells and their graphical representations. This tutorial shows the following examples:
Uses vhdl2vdb to create a precompiled library and rtl2zdb to use this library in a VHDL design. |
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Uses edif2zdb to generate a ZDB Binfile from an EDIF design. |
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Uses liberty2zdb to create library cells from Synopsys Liberty file format and verilog2zdb to parse a Verilog design. |
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Uses spice2zdb to create library cells from Spice and verilog2zdb to parse a Verilog design. |
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Shows the usage of sym2zdb and zdb2sym. |
VHDL Library Example
When processing a VHDL design the libraries normally are precompiled in the installation tree.
If user defined libraries are needed, they can be created with the vhdl2vdb tool.
As an example we compile the std_logic_1164.vhd
into a local library and use it for a small example design delta0.vhd
parsed with rtl2zdb.
vhdl2vdb -vhdl93 -library ieee -unit std_logic_1164 \ -vhdlLibPath ./mylibs vhdl_packages/vhdl93/std_1164.vhd rtl2zdb -vhdlLibPath ./mylibs demo/rtl/delta0/delta0.vhd -o design.zdb starvisionpro -binfile design.zdb
Edif2zdb Example
In this example we create a ZDB Binfile from an EDIF design, using edif2zdb.
The generated ZDB Binfile design.zdb
is then used for display in StarVision PRO.
edif2zdb -o design.zdb -symlib demo/edif/generic.sym demo/edif/gl85.edf starvisionpro -binfile design.zdb
Synopsys Liberty File Example
In this example we create a library lib.zdb
from the Synopsys .lib file example.lib
with the help of liberty2zdb.
It is referenced in a Verilog design example.v
parsed with verilog2zdb.
The generated design output file design.zdb
is then used for display in StarVision PRO.
liberty2zdb demo/api/cust4/example.lib -o lib.zdb verilog2zdb -binlib lib.zdb demo/api/cust4/example.v -o design.zdb starvisionpro -binfile design.zdb
Spice Library Example
In this example we create a library with Spice cells lib.zdb
by using spice2zdb.
It is referenced in a Verilog design mux4bit.v
by the parser rtl2zdb.
The graphical representation of the cells comes from the symlib file mux4bit.sym
.
The generated design output file design.zdb
is then used for display in StarVision PRO.
In this example mux4bit.v
has "empty" module definitions already defined.
These are overwritten by the Spice library and are only needed, if the file needs to be parsed standalone.
spice2zdb -hspice -power VDD -ground VSS demo/starvision/mux4bit/mux4bit.sp -o lib.zdb rtl2zdb -binlib lib.zdb -symlib demo/starvision/mux4bit/mux4bit.sym \ demo/starvision/mux4bit/mux4bit.v -o design.zdb starvisionpro -binfile design.zdb
Sym2zdb and Zdb2sym Example
In this example we create a library with cells (and symbol graphics) by using sym2zdb.
The generated binary library file lib.zdb
can then be used either with StarVision PRO or a batch parser to add a symbol shape to a primitive or module defined in the input file.
sym2zdb -o lib.zdb symutils/symlib/generic.sym
The next example shows the extraction of symbol graphics from an existing binary database file.
Here the lib.zdb
, which was created in the code above, is used to create the symlib file lib.sym
.
zdb2sym -o lib.sym lib.zdb