Other Paused Blocks

Basic blocks

Only basic blocks have simulation functions. But not all visible blocks in Activate models are basic blocks. Examples include virtual blocks and super blocks. In the list of blocks in the debugger dialog box, the location of a basic block inside a super block is indicated by a slash symbol. For example, SuperBlock/Integral.

For example, the SquareWaveGenerator block is a library super block whose diagram includes basic blocks. The debugger can pause in the basic blocks inside this super block and you can see the basic blocks in the list of blocks in the debugger.

Some library super blocks cannot be inlined in the model because their underlying diagram is created programmatically. In this case, the blocks inside have no graphical representation. Normally, pauses are indicated in the model diagram by an icon on the puased block that show the corresponding phase. When such a block is paused in, you can identify the parent diagram in most cases.

There are exceptions where no icon is shown during a pause, such as if a new basic block is added to the diagram by the compiler. For example, all Sampleclock blocks are replaced by the compiler with a single basic block, VssVirtualSampleClock1. When this block is paused, no icon is shown.

FMU and Modelica blocks

FMU and Modelica blocks are not basic blocks, but consist of basic blocks placed in a super block.

An FMU block consists of a central block and satellite blocks for each output. These component basic blocks can be paused during debugging.

Atomic super blocks

Atomic super blocks are compiled and replaced by single basic blocks during compilation. They are seen as basic blocks by the Activate debugger. The blocks inside them are not called during simulation and are not seen during debugging.