The Verilog Netlist Parser
This document describes the function of the software unit that reads Verilog netlist files and stores the connectivity (with parameters) in the hierarchical database ZDB for later processing.
Overview
Introduction
In addition of using the StarVision PRO GUI to read Verilog netlist files either the stand alone binary verilog2zdb
or the Tcl command zverilog
can be used.
The verilog2zdb
binary reads the given Verilog files and creates a binfile containing the connectivity of the input file:
verilog2zdb -o binfile.zdb <OPTIONS> <FILE.V>
The zverilog
Tcl command reads the given Verilog files and returns the created in-memory database:
set db [zverilog <OPTIONS> <FILE.V>]
The Tcl command is available in the Console window of the StarVision PRO GUI
and in the starsh
shell
.
This document describes the usage of this flow.
Options
Option | Parameters | Description |
---|---|---|
|
Read cmdline arguments from file. |
|
|
Open this binfile as a precompiled library. |
|
|
Stop on errors during parsing. |
|
|
Connect matching net by name, i.e. don’t route it. |
|
|
Create buses for ports with Verilog conform, consecutive numbering. |
|
|
Create hierarchy from flat instance names. Split the instance names at the given hierarchy separator. If the given hierarchy separator character is an empty string then the hierarchy separator character is guessed. |
|
|
Create unique nets for all constants. |
|
|
Enable a specific debug flag. |
|
|
Define a Verilog macro on the command line. |
|
|
Define Verilog macros on the command line. |
|
Don’t cut long filenames in messages. |
||
|
Read Verilog fileset file. The files in the fileset are relative to the fileset file. |
|
|
Read Verilog fileset file. Files in the fileset are relative to the current working directory. |
|
Overwrite existing symbols with the symbols from the given symbol library files (option -symlib). |
||
|
Define global Verilog include files. Global includes are processed before any other source files (this option can be repeated multiple times). |
|
|
Guess buses based on net and port names with a bit subscript enclosed in the given 'open' and 'close' characters. |
|
|
Guess instance arrays based on instance names with a bit subscript enclosed in the given 'open' and 'close' characters. |
|
Print a help text with a short description of each option. |
||
|
Set the desired hierarchy separator 'hiersepchar' of your choice. Any character can be used. To be able to identify the hierarchy separator, a character that is not already used in an identifier should be used. |
|
|
Define an include directory (this option can be repeated multiple times). |
|
|
Define include directories. |
|
|
Level of verbosity for issued messages. |
|
|
Compile the given files into an already existing database. |
|
|
Define the file name extensions for the -y option. |
|
Append to logfile. |
||
|
Generate log file. |
|
|
Matching files are structural Verilog files. |
|
Don’t search for a hierarchy separator. |
||
Print no greeting message. |
||
|
Name of the zdb output binfile. |
|
|
Toggle pedantic language checking mode (in relaxed mode some errors are just warnings and some warnings are suppressed). |
|
|
Preserve assignments in the netlist. |
|
Print progress information. |
||
|
Replace odd number of INVs in a chain by one INV and remove an even number of INVs in a chain. |
|
|
Remove all BUF and WIDE_BUF instances and merge the connected nets. |
|
|
Suffix for renaming duplicate cells. |
|
|
Resolve duplicate cells. If "off" all duplicate cells are renamed. |
|
|
Create source code references. |
|
|
Suppress messages which match pattern. |
|
Preload symbol library file(s) given with the -symlib option. |
||
|
Specify a symbol library file. |
|
|
Define SystemVerilog file name extensions. |
|
|
Specify a directory for temporary files. |
|
Print CPU time consumption (requires enabled progress updates). |
||
|
Define this module as the top module. If * is set, then all unreferenced cells are used as top. |
|
|
Read <libfile> as Verilog library file. |
|
Validate DB before creating the zdb output file. |
||
|
Define Verilog 1995 file name extensions. |
|
|
Define Verilog 2001 file name extensions. |
|
|
Wait 'sec' seconds for a license. If the value is -1 then the started tool will not wait for the next free license. Use a value of 0 to wait forever. |
|
|
Read files matching the extension given with +libext+ from the specified directory as Verilog library files. |