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89 | ###############################################################################
# Copyright (c) 2020-2024 by Altair Engineering, Inc.
# All rights reserved.
#
# Altair Engineering, Inc. makes this software available as part of the Vision
# tool platform. As long as you are a licensee of the Vision tool platform
# you may make copies of the software and modify it to be used within the
# Vision tool platform, but you must include all of this notice on any copy.
# Redistribution without written permission to any third party, with or
# without modification, is not permitted.
# Altair Engineering, Inc. does not warrant that this software is error free
# or fit for any purpose. Altair Engineering, Inc. disclaims any liability for
# all claims, expenses, losses, damages and costs any user may incur as a
# result of using, copying or modifying the software.
# =============================================================================
# @userware
# Compile a Design
# @section
# Miscellaneous Userware Examples
# @description
# Example Tcl script to compile all HDL design files into an
# in-memory (ZDB) database to be used with the Vision SDT platform.
# In the binary directory (linux64 or win64) of the Vision platform
# package you can find the starsh binary. This is a Tcl shell extended
# by all HDL parsers provided by the Vision platform.
# Either use the option -help to get a list of all possible options or
# see doc/parser/*parser.html for a more detailed description of the
# parser options.
# @files
# cust33/compileDesign.tcl
# @tag
# binfile batch
###############################################################################
##
# Create an empty database
#
set db [zdb new]
##
# Read Liberty
# -=-=-=-=-=-=
# The Liberty parser can render nice symbol shapes based on the Boolean
# equation at the output port function.
# In addition the clock cell and clock port information is extracted from the
# Liberty file(s). This is essential for running clock tree related API script
# on netlist files.
#
zliberty -into $db <OPTIONS> <FILE(S)>
##
# Read Verilog Netlist
# -=-=-=-=-=-=-=-=-=-=
# For performance reasons we provide a special Verilog netlist parser.
# This parser supports the Verilog IEEE-1364-1995 standard (aka. structural
# Verilog).
#
zverilog -into $db <OPTIONS> <FILE(S)>
##
# Read RTL Verilog and/or VHDL
# -=-=-=-=-=-=-=-=-=-=-=-=-=-=
# The RTL parser fully supports all versions of Verilog (including System
# Verilog and Verilog AMS) as well as all flavors of VHDL.
#
zrtl -into $db <OPTIONS> <FILE(S)>
##
# Save a Binfile
# -=-=-=-=-=-=-=
# Now the final design is stored in the in-memory (ZDB) database.
# This database can be saved as a binfile "design.zdb" for storage or further
# usage in the GUI or batch processing.
#
$db save design.zdb
##
# Work with the database
# -=-=-=-=-=-=-=-=-=-=-=
# The in-memory database can also be processed directly without saving a
# binfile using the '$db' Tcl API.
# Please use doc/api/index.html for a starting document on API commands.
#
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