Mixing Verilog and VHDL

SpiceVision PRO allows for mixing Verilog and VHDL design files.

All used example files can be found in the demo/rtl/mixed folder in the SpiceVision PRO directory.

Instantiating a VHDL Entity in a Verilog Module

A VHDL entity can be instantiated like any other verilog module. However, since a VHDL entity can have multiple architectures, the required architecture name can be specified as entity_name(arch_name). If no architecture is specified, the last defined architecture is chosen.

Example

A VHDL full adder with two architectures (structural and dataflow):

-- adder.vhdl

entity full_adder is
    port(a, b, cin: in  bit;
         sum, cout: out bit);
end full_adder;

architecture structural of full_adder is
component half_adder
    port(a, b:      in  bit;
         sum, cout: out bit);
end component;

signal u0_cout, u0_sum, u1_cout: bit;

begin
    u0: half_adder port map (a => a,      b => b,   sum => u0_sum, cout => u0_cout);
    u1: half_adder port map (a => u0_sum, b => cin, sum => sum,    cout => u1_cout);

    cout <= u0_cout or u1_cout;
end structural;

architecture dataflow of full_adder is
begin
  sum <=  ((not cin) and (not a) and      b ) or
          ((not cin) and      a  and (not b)) or
          (     cin  and (not a) and (not b)) or
          (     cin  and      a  and      b );

  cout <= ((not cin) and      a  and      b ) or
          (     cin  and (not a) and      b ) or
          (     cin  and      a  and (not b)) or
          (     cin  and      b  and      b );
end dataflow;

A Verilog top module instantiating three full adders: the first instantiation explicitly selects the structural architecture (please note the backslash-escaped module name \full_adder(structural) to avoid Verilog syntax errors), the second instantiation explicitly selects the dataflow architecture, and the third instantiation does not specify any architecture, but gets the dataflow variant, because it is declared last in the VHDL file.

// top.v

module top (a, b, cin, sum0, cout0, sum1, cout1, sum2, cout2);
    input a, b, cin;
    output sum0, cout0;
    output sum1, cout1;
    output sum2, cout2;

    // explicitly select the 'structural' architecture
    \full_adder(structural)  adder_explicitly_struct (a, b, cin, sum0, cout0);

    // explicitly select the 'dataflow' architecture
    \full_adder(dataflow)  adder_explicitly_dataflow (a, b, cin, sum1, cout1);

    // just select the last defined architecture
    full_adder adder_last_defined (a, b, cin, sum2, cout2);
endmodule

The example can be loaded into SpiceVision PRO with

Instantiating a Verilog Module in a VHDL Architecture

A Verilog module can be instantiated either by a direct entity instantiation or through a component or configuration, just like a VHDL entity.

Example

A full adder in Verilog:

// adder.v

module full_adder (a, b, cin, sum, cout);
    input a, b, cin;
    output sum, cout;

    assign sum = a ^ b ^ cin;
    assign cout = ((a ^ b) & cin) | (a & b);
endmodule

A VHDL entity instantiating two Verilog full adders: the first instantiation is a direct instantiation that uses the full Verilog module name including its library (work.full_adder), for the second instantiation a new component (component full_adder) is defined in the architecture.

-- top.vhdl

entity top is
    port(a, b, cin: in  bit;
         sum0, cout0: out bit;
         sum1, cout1: out bit);
end top;

architecture arch of top is
    -- New component
    component full_adder is
        port(a, b, cin: in  bit;
             sum, cout: out bit);
    end component full_adder;
begin
    -- Direct entity instantiation
    a1 : entity work.full_adder
        port map (a => a, b => b, cin => cin, sum => sum0, cout => cout0);

    -- Using component instantiation
    a2 : full_adder
        port map (a => a, b => b, cin => cin, sum => sum1, cout => cout1);
end arch;

The example can be loaded into SpiceVision PRO with