This tutorial demonstrates the usage of the Clock Domain Analyzer window by running an example from the demo/rtl/ directory.
For more general information please consult the Quickstart guide or the Reference Manual.
The following steps are based on the design stored in demo/rtl/wb_sys/.
The design files are listed in the predefined fileset demo/rtl/wb_sys/conmax_top.f.
If you have trouble loading this fileset please consult the Quickstart guide or the Open Files manual first.
Clock Domain
After loading the fileset conmax_top.f from the directory demo/rtl/wb_sys/ open the Clock Domain Analyzer window from the Tools main menu.
Since the clock domain algorithms rely on correct clocked cells information, please revise the Clocked Cells settings.
If the clocked cells settings are correct then you can see the calculated clock domain information in a graphical way.
Depending on the design size this can take some time.
Each clock domain is represented by a box with the total number of connections to clocked cells inside.
Use the "Highlight All" button to highlight each clock domain in a different color.
If you go to the Schematic window and turn on the greymode then it is very easy to identify the clock signals.
You can double click on the graphical representation of a clock domain to load and display the clock domain in the Cone window. The following image shows the top part of the displayed clock domain.
In each hierarchy level only one representative of a clocked cell is displayed and the total count of clocked cells in each hierarchy level is annotated at this cell.
Clock Domain Crossings
A click on the "Add CDC" button allows you to find all crossings between the various clock domains.
You can select two or more clock domains to limit the number of source and target domains. Multiple objects can be selected by holding down the Ctrl key.
The result will look like the following image.
The transitions between the domains are indicated by arrows. An arrow with a thin line means there is only a little bit of logic between the two domains. An arrow with a thick line indicates that there is a lot of logic between the two domains.
The nets connecting the logic between two domains can also be highlighted. For this purpose, double click on the transition arrow of interest. This will load and show the logic in the Cone window. This transition arrow will be shown as a dotted line afterwards. In the image above the transition between 'mrx_clk_pad_i domain' and 'mtx_clk_pad_i domain' is highlighted in purple. Now you can double click on the output pin 'q' of the light green highlighted Flip-Flop named 'PauseTimerEq0_sync1' on the right side to see that this transition is synchronized by a second Flip-Flop of the same color. The contents of your Cone window will look like the above image.
Clocked Cells
This section explains how to manually specify or add additional clocked cells. When reading RTL, the parser knows which cells are clocked and automatically adds them to the list of clocked cells. You can use this dialog to specify additional cells as clocked cells.
If you read a gatelevel netlist then the parser does not know anything about clocked cells. In that case you have to use this dialog to specify all clocked cells and the corresponding clocked ports in order to use the Clock Domain Analyzer window.