Introduction

This document describes the "Primitive Functions" of the DataBase API; The primitives in the design hierarchy are usually primitive objects with a known function (e.g. AND, NOR, etc.). However, some algorithms, e.g. Cone Extraction will not traverse the design hierarchy tree down to the primitives but may "stop" at bus-level (sometimes called "operator-level") where the function of a module is known (these modules are treated as "primitives" for that algorithm).

Overview

Here is an overview of the various module and primitive types. The function is returned by primFuncOf. The flags are returned or set by the flag command.

OID Type Function Has Sub-Netlist Flags Description Index

module

NONE

Yes

Any hierarchy module that is defined by the lower-level netlist only.

#1

No

Empty module.

#2

undefined

Undefined module (= blackbox module); ports may have unknown directions.

#3

Yes/No

libcell

Any library cell, normally with lower-level netlist (eventually with attached symbol shape).

#4

some function
(e.g. WIDE_BUF)

Yes/No

Module with a known (bus-level) function (sometimes called "operator"), may have an implementing lower-level netlist (redundant data).

#5

primitive

some function
(e.g. NAND)

No

Primitive with a known function (similar to #5).

#6

UNKNOWN

No

Unknown primitive from a source like EDIF that does not know anything about library cells (similar to #2).

#7

The functions NONE and UNKNOWN are identical, NONE is used at modules and UNKNOWN at primitives.

Note that some GUI features, like the Tree window, traverse the design hierarchy down to the real primitive objects; that means, it distinguishes modules (#1 to #5) from primitives (#6 to #7). However some algorithms may stop as soon as a function is known, and therefore consider #5 to #7 as "primitives"; other algorithms may stop at library cells and consider #4 to #7 as "primitives".

For a better understanding, here is what the various parsers create:

Parser Module/Primitive Objects Created

liberty2zdb, lib2zdb

Creates library cells (#4) with symbol shape definition and with optional content lower-level netlist consisting of operators (#5) and primitives (#6).

verilog2zdb, rtl2zdb

Creates hierarchy modules (#1) with netlists consisting of operators (#5) and primitives (#6); if a module is defined inside `celldefine or read from a -v or -y file, then it is flagged as library cell (#4); undefined instantiation creates an undefined module (#3).

edif2zdb

Creates hierarchy modules (#1) and unknown primitives (#7).

spice2zdb

Creates hierarchy modules (#1) and Spice primitives (#6).

symlib2zdb

Creates library cells (#4) with symbol shape definition.

lef2zdb

Creates empty library cells (#4).

def2zdb

Creates hierarchy modules (#1) with netlists of cells (e.g. from lef2zdb).

Port Function

This database applies the same port-order rules to Primitives as well as to Modules with defined function. That means, if a function is defined, then the number of ports and their directions and their function is ruled by the database built-in specification, as defined in this document. The database enforces that those rules are not violated.

Ordinary modules (with function = NONE) as well as primitives with UNKNOWN function have no port-restrictions at all (any number of ports and portBuses in arbitrary order). All ports can be bubbled/negated.

Primitives (as well as modules) with a known function define the direction and function of their ports by the port-order. For each function, only a certain number and order of the ports is possible. Also depending on the function, some ports may be bubbled/negated (details below).

All port names are arbitrary (the names in this document are chosen only for better understanding). Of course, all port names within a primitive or module are unique.

Load and Retrieve the Port Direction

For UNKNOWN primitives and modules without a function (function = NONE), loading a port must specify a port direction. However, for a primitive or module with a known function, loading a port can (and should) use a * for the port direction (to apply the built-in direction) — or if a direction is specified, then it must match the built-in specification or an error is returned. Independent from the function, the command directionOf returns the correct direction.

Bubbled Ports

Some ports or portBuses can be bubbled to define negated port functions (and to display them bubbled). If so, then the command directionOf will append .neg to the returned port direction, e.g. input.neg (instead of input). The .neg extension can also be used for API-loading, including *.neg for known functions, as described in the tables below.

Definition of Primitive Functions

Special Primitives

UNKNOWN

Description

An unknown function with an arbitrary number and order of input/output/inout ports (no restrictions).

A mix of single-bit ports and portbuses with arbitrary widths is supported.

All ports and portbuses can be bubbled.

Ports
No Name Type

…​

…​

…​

Gate-Level Functions

Description

The primitive functions below describe gate-level functions.

The function names and port orders partly follow the Verilog gate definitions.

All ports are single-bit (except for UNKNOWN).

On the API-level, a cell’s function is specified in the corresponding load command call ($db load primitive $name $function …​ for primitives, $db load module $name ?-primfunc $function? …​ for modules), while the primitive function of a cell can be queried using the primFuncOf command ($db primFuncOf $cell).

Combinational Gates

AND

Description

Boolean "AND" function.

The first port is the output, followed by one or more input ports.

The input ports can be bubbled.

Ports
No Name Type

0

Y

output

1

A

input

2

B

input

…​

…​

input

NAND

Description

Boolean "NAND" function.

The first port is the output, followed by one or more input ports.

The input ports can be bubbled.

Ports
No Name Type

0

Y

output

1

A

input

2

B

input

…​

…​

input

OR

Description

Boolean "OR" function.

The first port is the output, followed by one or more input ports.

The input ports can be bubbled.

Ports
No Name Type

0

Y

output

1

A

input

2

B

input

…​

…​

input

NOR

Description

Boolean "NOR" function.

The first port is the output, followed by one or more input ports.

The input ports can be bubbled.

Ports
No Name Type

0

Y

output

1

A

input

2

B

input

…​

…​

input

XOR

Description

Boolean "XOR" function.

The first port is the output, followed by one or more input ports.

The input ports can be bubbled.

Example
$db load primitive xor4 XOR
$db load port Y output
$db load port A input
$db load port B input.neg
$db load port C input.neg
$db load port D input
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

…​

…​

input

XNOR

Description

Boolean "XNOR" function.

The first port is the output, followed by one or more input ports.

The input ports can be bubbled.

Ports
No Name Type

0

Y

output

1

A

input

2

B

input

…​

…​

input

BUF

Description

(Multi-output) buffer.

All ports but the last port are outputs, the last port is the input (as Verilog defines 'buf').

Ports
No Name Type

0

Y

output

…​

…​

output (optional)

last

I

input

FORCE

Description

(Multi-output) "forced" buffer, typically generated from a "force"-type assignment in Verilog/VHDL.

All ports but the last port are outputs, the last port is the input.

Ports
No Name Type

0

Y

output

…​

…​

output (optional)

last

I

input

INV

Description

(Multi-output) Boolean "Inverter" function.

All ports but the last port are outputs, the last port is the input (as Verilog defines 'inv').

Ports
No Name Type

0

Y

output

…​

…​

output (optional)

last

I

input

MUX

Description

2-input multiplexer.

The first port is the output, the second and third ports are the inputs A and B, the fourth port is the select port Sel; if Sel is 0, A is switched to the output, if Sel is 1, B is switched to the output.

Ports
No Name Type

0

Y

output

1

A

input

2

B

input

3

Sel

input

ADD

Description

1-bit full adder with carry-in and carry-out.

The first port is the sum output, the second port is carry-out, the third and fourth ports are the adder inputs, and the fifth port is the carry-in.

Example
$db load primitive adder ADD
$db load port Y  output
$db load port Co output
$db load port A  input
$db load port B  input
$db load port Ci input
Ports
No Name Type

0

Y

output

1

Co

output

2

A

input

3

B

input

4

Ci

input

State Elements

DFF

Description

Simple flip-flop.

The first port is the output, the second port is the data input, the third port is the clock (active on positive edge), the optional fourth and fifth ports are reset and set inputs. The clock, set and reset inputs may be bubbled.

Ports
No Name Type

0

Y

output

1

D

input

2

Clk

input

3

Reset

input (optional)

4

Set

input (optional)

DFFN

Description

Simple flip-flop with a non-inverting output and an inverting output.

The first port is the non-inverting output, The second port is the inverting output, the third port is the data input, the fourth port is the clock (active on positive edge), the optional fifth and sixth ports are reset and set inputs. The clock, set and reset inputs may be bubbled.

Ports
No Name Type

0

Y

output

1

YN

output

2

D

input

3

Clk

input

4

Reset

input (optional)

5

Set

input (optional)

DLATCH

Description

Simple latch.

The first port is the output, the second port is the data input, the third port is the enable input, the optional fourth and fifth ports are reset and set inputs. The enable, set and reset inputs may be bubbled.

Ports
No Name Type

0

Y

output

1

D

input

2

En

input

3

Reset

input (optional)

4

Set

input (optional)

DLATCHN

Description

Simple latch with a non-inverting output and an inverting output.

The first port is the non-inverting output, The second port is the inverting output, the third port is the data input, the fourth port is the enable input, the optional fifth and sixth ports are reset and set inputs. The enable, set and reset inputs may be bubbled.

Ports
No Name Type

0

Y

output

1

YN

output

2

D

input

3

En

input

4

Reset

input (optional)

5

Set

input (optional)

DFFCV

Description

Condition/value flip-flop.

The first port is the output, the second port is the data input, the third port is the clock (active on positive edge), the fourth and fifth ports are condition and value inputs. The clock may be bubbled.

Ports
No Name Type

0

Y

output

1

D

input

2

Clk

input

3

Condition

input

4

Value

input

DLATCHCV

Description

Condition/value latch.

The first port is the output, the second port is the data input, the third port is the enable input, the fourth and fifth ports are condition and value inputs. The enable input may be bubbled.

Ports
No Name Type

0

Y

output

1

D

input

2

En

input

3

Condition

input (optional)

4

Value

input (optional)

Other Functions

BUFIF0

Description

A tri-state buffer.

The first port is the output, the second port is the input, the third port is the control input.

If the control input is 1, the buffer is set to high-impedance state (as Verilog defines bufif0).

Ports
No Name Type

0

Y

output

1

I

input

2

Ctrl

input

BUFIF1

Description

A tri-state buffer.

The first port is the output, the second port is the input, the third port is the control input.

If the control input is 0, the buffer is set to high-impedance state (as Verilog defines bufif1).

Ports
No Name Type

0

Y

output

1

I

input

2

Ctrl

input

INVIF0

Description

A tri-state inverting buffer.

The first port is the output, the second port is the input, the third port is the control input.

If the control input is 1, the buffer is set to high-impedance state (as Verilog defines notif0).

Ports
No Name Type

0

Y

output

1

I

input

2

Ctrl

input

INVIF1

Description

A tri-state inverting buffer.

The first port is the output, the second port is the input, the third port is the control input.

If the control input is 0, the buffer is set to high-impedance state (as Verilog defines notif1).

Ports
No Name Type

0

Y

output

1

I

input

2

Ctrl

input

TRAN

Description

A transfer gate.

This primitive has exactly two inout (bidirectional) ports (as Verilog defines tran).

Ports
No Name Type

0

P1

inout

1

P2

inout

TRANIF0

Description

A bi-directional transistor (low).

This primitive has two inout (bidirectional) ports, and a control input (as Verilog defines tranif0).

Ports
No Name Type

0

P1

inout

1

P2

inout

2

Ctrl

input

TRANIF1

Description

A bi-directional transistor (high).

This primitive has two inout (bidirectional) ports, and a control input (as Verilog defines tranif1).

Ports
No Name Type

0

P1

inout

1

P2

inout

2

Ctrl

input

RTRANIF1

Description

A resistive transistor (high).

This primitive has two inout (bidirectional) ports, and a control input (as Verilog defines rtranif1).

Ports
No Name Type

0

P1

inout

1

P2

inout

2

Ctrl

input

GNMOS

Description

A gate-level NMOS transistor.

(as Verilog defines nmos)

Example
$db load primitive gnmos GNMOS
$db load port Y *
$db load port A *
$db load port C *
Ports
No Name Type

0

Y

output

1

I

input

2

Ctrl

input

GPMOS

Description

A gate-level PMOS transistor.

(as Verilog defines pmos)

Example
$db load primitive gpmos GPMOS
$db load port Y *
$db load port A *
$db load port C *
Ports
No Name Type

0

Y

output

1

I

input

2

Ctrl

input

GRNMOS

Description

A gate-level resistive NMOS transistor.

(as Verilog defines rnmos)

Example
$db load primitive grnmos GRNMOS
$db load port Y *
$db load port A *
$db load port C *
Ports
No Name Type

0

Y

output

1

I

input

2

Ctrl

input

GRPMOS

Description

A gate-level resistive PMOS transistor.

(as Verilog defines rpmos)

Example
$db load primitive grpmos GRPMOS
$db load port Y *
$db load port A *
$db load port C *
Ports
No Name Type

0

Y

output

1

I

input

2

Ctrl

input

GCMOS

Description

A combination of gate-level NMOS and PMOS transistors with common data input and output ports.

(as Verilog defines cmos)

Example
$db load primitive gcmos GCMOS
$db load port Y *
$db load port A *
$db load port nC *
$db load port C *
Ports
No Name Type

0

Y

output

1

A

input

2

nCtrl

input

3

Ctrl

input

GRCMOS

Description

A combination of gate-level resistive NMOS and PMOS transistors with common data input and output ports.

(as Verilog defines rcmos)

Example
$db load primitive grcmos GRCMOS
$db load port Y *
$db load port A *
$db load port nC *
$db load port C *
Ports
No Name Type

0

Y

output

1

A

input

2

nCtrl

input

3

Ctrl

input

PULLUP

Description

A "pull-up" resistor.

Example
$db load primitive pu PULLUP
$db load port a *
Ports
No Name Type

0

pt1

output

PULLDOWN

Description

A "pull-down" resistor.

Example
$db load primitive pd PULLDOWN
$db load port a *
Ports
No Name Type

0

pt1

output

Bus-Level Functions

Description

The primitive functions below describe bused functions (word-level).

The function is defined e.g. by the load API and returned by primFuncOf.

All ports are usually a mix of multi-bit buses and single-bits. In the table below, the column "Ports/Type" uses a square-bracket notation to identify buses (portBus instead of port); Buses which are required to have the same width use the same index denominator, while buses with potentially different widths use different index denominators (e.g. [n] and [m]).

Reducing Functions (n to 1)

REDUCE_AND

Description

Bus-input reducing Boolean "AND" function.

The first port is the output, followed by one input portbus of arbitrary width.

Y = AND(A[0], …​, A[n-1])

Ports
No Name Type

0

Y

output

1

A

{input[n]}

REDUCE_NAND

Description

Bus-input reducing Boolean "NAND" function.

The first port is the output, followed by one input portbus of arbitrary width.

Y = NAND(A[0], …​, A[n-1])

Ports
No Name Type

0

Y

output

1

A

{input[n]}

REDUCE_OR

Description

Bus-input reducing Boolean "OR" function.

The first port is the output, followed by one input portbus of arbitrary width.

Y = OR(A[0], …​, A[n-1])

Ports
No Name Type

0

Y

output

1

A

{input[n]}

REDUCE_NOR

Description

Bus-input reducing Boolean "NOR" function.

The first port is the output, followed by one input portbus of arbitrary width.

Y = NOR(A[0], …​, A[n-1])

Ports
No Name Type

0

Y

output

1

A

{input[n]}

REDUCE_XOR

Description

Bus-input reducing Boolean "XOR" function.

The first port is the output, followed by one input portbus of arbitrary width.

Y = XOR(A[0], …​, A[n-1])

Ports
No Name Type

0

Y

output

1

A

{input[n]}

REDUCE_XNOR

Description

Bus-input reducing Boolean "XNOR" function.

The first port is the output, followed by one input portbus of arbitrary width.

Y = XNOR(A[0], …​, A[n-1])

Ports
No Name Type

0

Y

output

1

A

{input[n]}

Wide Functions (n to n)

WIDE_AND

Description

Wide Boolean "AND" function.

The first portbus is the output bus, it is followed by an arbitrary number of input portbuses.

All buses must have the same width.

The input buses may be bubbled, indicating a negation of the complete input bus.

Y[0] = AND(A[0], B[0], ...)
Y[1] = AND(A[1], B[1], ...)
...
Y[n-1] = AND(A[n-1], B[n-1], ...)
Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

2

B

{input[n]}

…​

…​

{input[n]}

WIDE_NAND

Description

Wide Boolean "NAND" function.

The first portbus is the output bus, it is followed by an arbitrary number of input portbuses.

All buses must have the same width.

The input buses may be bubbled, indicating a negation of the complete input bus.

Y[0] = NAND(A[0], B[0], ...)
Y[1] = NAND(A[1], B[1], ...)
...
Y[n-1] = NAND(A[n-1], B[n-1], ...)
Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

2

B

{input[n]}

…​

…​

{input[n]}

WIDE_OR

Description

Wide Boolean "OR" function.

The first portbus is the output bus, it is followed by an arbitrary number of input portbuses.

All buses must have the same width.

The input buses may be bubbled, indicating a negation of the complete input bus.

Y[0] = OR(A[0], B[0], ...)
Y[1] = OR(A[1], B[1], ...)
...
Y[n-1] = OR(A[n-1], B[n-1], ...)
Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

2

B

{input[n]}

…​

…​

{input[n]}

WIDE_NOR

Description

Wide Boolean "NOR" function.

The first portbus is the output bus, it is followed by an arbitrary number of input portbuses.

All buses must have the same width.

The input buses may be bubbled, indicating a negation of the complete input bus.

Y[0] = NOR(A[0], B[0], ...)
Y[1] = NOR(A[1], B[1], ...)
...
Y[n-1] = NOR(A[n-1], B[n-1], ...)
Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

2

B

{input[n]}

…​

…​

{input[n]}

WIDE_XOR

Description

Wide Boolean "XOR" function.

The first portbus is the output bus, it is followed by an arbitrary number of input portbuses.

All buses must have the same width.

The input buses may be bubbled, indicating a negation of the complete input bus.

Y[0] = XOR(A[0], B[0], ...)
Y[1] = XOR(A[1], B[1], ...)
...
Y[n-1] = XOR(A[n-1], B[n-1], ...)
Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

2

B

{input[n]}

…​

…​

{input[n]}

WIDE_XNOR

Description

Wide Boolean "XNOR" function.

The first portbus is the output bus, it is followed by an arbitrary number of input portbuses.

All buses must have the same width.

The input buses may be bubbled, indicating a negation of the complete input bus.

Y[0] = XNOR(A[0], B[0], ...)
Y[1] = XNOR(A[1], B[1], ...)
...
Y[n-1] = XNOR(A[n-1], B[n-1], ...)
Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

2

B

{input[n]}

…​

…​

{input[n]}

WIDE_BUF

Description

Wide buffer.

The first portbus is the output bus, it is followed by an input portbus.

The buses must have the same width.

Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

WIDE_INV

Description

Wide Boolean inverter.

The first portbus is the output bus, it is followed by an input portbus.

The buses must have the same width.

Y[0] = INV(A[0])
Y[1] = INV(A[1])
...
Y[n-1] = INV(A[n-1])
Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

WIDE_TRI

Description

Wide tri-state buffer.

The first portbus is the output bus, it is followed by an input portbus and a single control port.

The buses must have the same width.

Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

2

Ctrl

input

Mixed Functions

WIDE_NTO1MUX

Description

Multi-input multiplexer.

The first portbus is the output bus, it is followed by an arbitrary number of input portbuses D0 …​ Dx, and a select input bus Sel.

All buses except Sel must have the same width.

Sel selects which input bus is switched to the output:

  • If Sel is 0, D0 is switched to the output,

  • if Sel is 1, D1 is switched to the output,

  • …​

  • if Sel is x, Dx is switched to the output.

Ports
No Name Type

0

Y

{output[n]}

1

D0

{input[n]}

2

D1

{input[n]}

…​

…​

…​

(x+1)

Dx

{input[n]}

(x+2)

Sel

{input[m]}

WIDE_MUX

Description

2-input bus multiplexer.

The first portbus is the output bus, it is followed by two input buses A and B, and a select input Sel.

All buses must have the same width.

Sel selects which input is switched to the output:

  • If Sel is 0, A is switched to the output,

  • if Sel is 1, B is switched to the output.

Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

2

B

{input[n]}

3

Sel

input

ADDER

Description

Multi-bit full adder with carry-in and carry-out.

The first portbus is the output bus, it is followed by the carry-out port; next are the two adder input buses, followed by the carry-in port.

The buses can have pairwise different widths.

Ports
No Name Type

0

Y

{output[o]}

1

Co

output

2

A

{input[m]}

3

B

{input[n]}

4

Ci

input

MULTIPLIER

Description

Arithmetic "MULTIPLIER" function.

The first portbus is the output bus, next are the two operand input buses.

The buses can have pairwise different widths.

Ports
No Name Type

0

Y

{output[o]}

1

A

{input[m]}

2

B

{input[n]}

POW

Description

Arithmetic "POW" function.

The first portbus is the output bus, next are the two operand input buses.

The buses can have pairwise different widths.

Ports
No Name Type

0

Y

{output[o]}

1

A

{input[m]}

2

B

{input[n]}

DIVIDER

Description

Arithmetic "DIVIDER" function.

The first portbus is the output bus, next are the two operand input buses.

The buses can have pairwise different widths.

Ports
No Name Type

0

Y

{output[o]}

1

A

{input[m]}

2

B

{input[n]}

MODULO

Description

Arithmetic "MODULO" function.

The first portbus is the output bus, next are the two operand input buses.

The buses can have pairwise different widths.

Ports
No Name Type

0

Y

{output[o]}

1

A

{input[m]}

2

B

{input[n]}

REMAINDER

Description

Arithmetic "REMAINDER" function.

The first portbus is the output bus, next are the two operand input buses.

The buses can have pairwise different widths.

Ports
No Name Type

0

Y

{output[o]}

1

A

{input[m]}

2

B

{input[n]}

SHIFT_LEFT

Description

Bitwise left shift.

The first portbus is the output bus, it is followed by the input bus, the shift amount input bus S, and a carry-in port.

All portbuses except S must have the same width.

Ports
No Name Type

0

Y

{output[n]}

1

I

{input[n]}

2

S

{input[m]}

3

Ci

input

SHIFT_RIGHT

Description

Bitwise right shift.

The first portbus is the output bus, it is followed by the input bus, the shift amount input bus S, and a carry-in port.

All portbuses except S must have the same width.

Ports
No Name Type

0

Y

{output[n]}

1

I

{input[n]}

2

S

{input[m]}

3

Ci

input

ROTATE_LEFT

Description

Bitwise left rotation.

The first portbus is the output bus, it is followed by the input bus, and the rotate amount input bus S.

All portbuses except S must have the same width.

Ports
No Name Type

0

Y

{output[n]}

1

I

{input[n]}

2

S

{input[m]}

ROTATE_RIGHT

Description

Bitwise right rotation.

The first portbus is the output bus, it is followed by the input bus, and the rotate amount input bus S.

All portbuses except S must have the same width.

Ports
No Name Type

0

Y

{output[n]}

1

I

{input[n]}

2

S

{input[m]}

LESSTHAN

Description

The arithmetic "less than" or "less or equal" operation.

The first port is the result output, followed by two input portbuses, and a carry-in.

Both portbuses may have different widths.

The carry-in selects the actual operation:

  • carry-in = 0 ⇒ "less than"

  • carry-in = 1 ⇒ "less or equal"

The result output can be bubbled.

Ports
No Name Type

0

O

output

1

A

{input[n]}

2

B

{input[m]}

3

Cin

input

NTO1MUX

Description

A portbus-input multiplexer with single bit output.

The first port is the output, the following two portbuses are the input portbus D, and the selection input Sel.

Sel selects which bit of D is switched to the output:

  • if Sel is 0, D[0] is switched to the output,

  • if Sel is 1, D[1] is switched to the output,

  • …​

  • if Sel is n-1, D[n-1] is switched to the output.

The portbuses may have different widths.

Ports
No Name Type

0

Y

output

1

D

{input[n]}

2

Sel

{input[m]}

SELECTOR

Description

A "selector" with single bit output, a portbus input A, and a selection input portbus Sel.

Both portbuses must have the same width.

Ports
No Name Type

0

Y

output

1

A

{input[n]}

2

Sel

{input[n]}

DECODER

Description

A "decoder".

The first portbus is the output, followed by an input portbus, and an optional control port.

The portbuses may have different widths.

If the control port is given, the decoder is actually an "enabled decoder", i.e. its output signals are "AND-ed" with the control signal.

Ports
No Name Type

0

Y

{output[n]}

1

A

{input[m]}

2

Ctrl

input (optional)

PRIO_SELECTOR

Description

A "priority selector".

The first port is the a single bit output, followed by an input portbus, a selection input portbus Sel, and a carry-in port.

The carry-in port is used as the "else value".

The portbuses must have the same width.

Ports
No Name Type

0

Y

output

1

A

{input[n]}

2

Sel

{input[n]}

3

Cin

input

WIDE_PRIO_SELECTOR

Description

A "wide priority selector".

The carry-in portbus is used as the "else value".

Ports
No Name Type

0

Y

{output[m]}

1

A0

{input[m]}

2

A1

{input[m]}

…​

…​

…​

n

AN

{input[m]}

2+n

Sel

{input[n]}

3+n

Cin

{input[m]}

PRIO_ENCODER

Description

A "priority encoder".

Ports
No Name Type

0

Y

{output[n+1]}

1

A

{input[n]}

WIDE_CASE_SELECT_BOX

Description

This primitive represents a "case statement".

Ports
No Name Type

0

out

{output[m]}

1

sel

{input[s]}

2

sel_val

{input[n*s]}

3

data

{input[n*m]}

4

default

{input[m]}

LUT

Description

A lookup table.

Ports
No Name Type

0

Y

output

1

D

{input[n]}

ABS

Description

The arithmetic "ABS" operation.

Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

MINUS

Description

The arithmetic "subtraction" operation.

The first portbus is the result output, followed by two input portbuses (the "minuend" and the "subtrahend").

All portbuses must have same width.

Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

2

B

{input[n]}

UMINUS

Description

The "unary minus" operation.

The first portbus is the result output, followed by one input portbus.

Both portbuses must have same width.

Ports
No Name Type

0

Y

{output[n]}

1

A

{input[n]}

EQUAL

Description

The "equal" operation.

The first port is the result output, followed by two input portbuses of equal width.

Ports
No Name Type

0

Y

output

1

A

{input[n]}

2

B

{input[n]}

NEQUAL

Description

The "not equal" operation.

The first port is the result output, followed by two input portbuses of equal width.

Ports
No Name Type

0

Y

output

1

A

{input[n]}

2

B

{input[n]}

WIDE_SELECTOR

Description

A bus selector.

Ports
No Name Type

0

Y

{output[n]}

1

D0

{input[n]}

…​

…​

…​

1+x

Dx

{input[n]}

2+x

Sel

{input[m]}

RAM Elements

RAM

Description

A generic RAM with unrestricted ports.

Ports
No Name Type

…​

…​

…​

DUAL_PORT_RAM

Description

A "dual port RAM";

The data ports (Y and D) must have equal widths, and the address ports (Wadr and Radr) must have equal widths.

Ports
No Name Type

0

Y

{output[n]}

1

D

{input[n]}

2

Wadr

{input[m]}

3

Radr

{input[m]}

4

Wen

input

READ_PORT

Description

A "read port" of a multi-port RamNet.

The RamNet port is normally connected to a net which interconnects all read/write-ports of the same RAM.

Ports
No Name Type

0

D

{output[m]}

1

Adr

{input[n]}

2

RamNet

input

3

Ren

input

WRITE_PORT

Description

A "write port" of a multi-port RamNet.

The RamNet port is normally connected to a net which interconnects all read/write-ports of the same RAM.

Ports
No Name Type

0

RamNet

output

1

Adr

{input[m]}

2

D

{input[n]}

3

Wen

input

CLOCKED_WRITE_PORT

Description

A "clocked write port" of a multi-port RamNet.

The RamNet port is normally connected to a net which interconnects all read/write-ports of the same RAM.

Ports
No Name Type

0

RamNet

output

1

Adr

{input[m]}

2

D

{input[n]}

3

Clk

input

4

Wen

input

Wide State Elements

WIDE_DFF

Description

A wide flip-flop.

Ports
No Name Type

0

Y

{output[n]}

1

D

{input[n]}

2

Clk

input

3

Reset

{input[n]} (optional)

4

Set

{input[n]} (optional)

WIDE_DLATCH

Description

A wide dlatch.

Ports
No Name Type

0

Y

{output[n]}

1

D

{input[n]}

2

En

input

3

Reset

{input[n]} (optional)

4

Set

{input[n]} (optional)

WIDE_DFFCV

Description

A wide condition/value flip-flop.

Ports
No Name Type

0

Y

{output[n]}

1

D

{input[n]}

2

Clk

input

3

Condition

{input[n]}

4

Value

{input[n]}

WIDE_DLATCHCV

Description

A wide condition/value dlatch.

Ports
No Name Type

0

Y

{output[n]}

1

D

{input[n]}

2

En

input

3

Condition

{input[n]}

4

Value

{input[n]}

Assertions

Description

The following primitive functions represent SystemVerilog Assertions (SVA), as created by our SystemVerilog front-end. All ports are single-bit.

Assertion Primitives (1 Input)

HDL_ASSERTION

Description

Generic HDL assertion.

Ports
No Name Type

0

A

input

SVA_IMMEDIATE_ASSERT

Description
assert <expr>
Ports
No Name Type

0

A

input

SVA_ASSERT

Description
assert property <expr>
Ports
No Name Type

0

A

input

SVA_COVER

Description
cover property <expr>
Ports
No Name Type

0

A

input

SVA_IMMEDIATE_COVER

Description
cover  #0 <expr>
Ports
No Name Type

0

A

input

SVA_ASSUME

Description
assume property <expr>
Ports
No Name Type

0

A

input

SVA_IMMEDIATE_ASSUME

Description
assume #0 <expr>
Ports
No Name Type

0

A

input

SVA_EXPECT

Description
expect property <expr>
Ports
No Name Type

0

A

input

Unary SVA Operators (1 Output, 1 Input)

SVA_POSEDGE

Description
posedge <expr>
Ports
No Name Type

0

Y

output

1

A

input

SVA_NOT

Description
not <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

SVA_FIRST_MATCH

Description
first_match <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

SVA_ENDED

Description
<seq_expr>.ended
Ports
No Name Type

0

Y

output

1

A

input

SVA_MATCHED

Description
<seq_expr>.matched
Ports
No Name Type

0

Y

output

1

A

input

SVA_CONSECUTIVE_REPEAT

Description
<seq_expr> [* <const_or_range_expr>]
Ports
No Name Type

0

Y

output

1

A

input

SVA_NON_CONSECUTIVE_REPEAT

Description
<seq_expr> [*= <const_or_range_expr>]
Ports
No Name Type

0

Y

output

1

A

input

SVA_GOTO_REPEAT

Description
<seq_expr> [*-> <const_or_range_expr>]
Ports
No Name Type

0

Y

output

1

A

input

SVA_MATCH_ITEM_TRIGGER

Description
(<sequence_expr>,<local_var>=<expr>)
Ports
No Name Type

0

Y

output

1

A

input

SVA_WITHIN_RANGE

Description
##[range] <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

SVA_STRONG

Description
strong (<seq_expr>)
Ports
No Name Type

0

Y

output

1

A

input

SVA_WEAK

Description
weak (<seq_expr>)
Ports
No Name Type

0

Y

output

1

A

input

SVA_RESTRICT

Description
restrict (<property_expr>)
Ports
No Name Type

0

Y

output

1

A

input

SVA_TRIGGERED

Description
<sequence_expr>.triggered
Ports
No Name Type

0

Y

output

1

A

input

SVA_NEXTTIME

Description
nexttime <property_expr>

or

nexttime [<constant_expr>] <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

SVA_S_NEXTTIME

Description
s_nexttime <property_expr>

or

s_nexttime [<constant_expr>] <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

SVA_ALWAYS

Description
always <property_expr>

or

always [<cycle_delay_constant_range_expr>] <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

SVA_S_ALWAYS

Description
s_always [<constant_range>] <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

SVA_S_EVENTUALLY

Description
s_eventually <property_expr>

or

s_eventually [<cycle_delay_constant_range_expr>] <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

SVA_EVENTUALLY

Description
eventually [<constant_range>] <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

Binary SVA Operators (1 Output, 2 Inputs)

SVA_AND

Description
<property_expr> and <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_OR

Description
<property_expr> or <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_SEQ_AND

Description
<seq_expr> and <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_SEQ_OR

Description
<seq_expr> or <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_EVENT_OR

Description

Event 'or' in the argument of a sequence or property, e.g.

@(posedge clk) seq1(in1 or in2);
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_OVERLAPPED_IMPLICATION

Description
<seq_expr> \|-> <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_NON_OVERLAPPED_IMPLICATION

Description
<seq_expr> \|=> <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_OVERLAPPED_FOLLOWED_BY

Description
<seq_expr> #-# <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_NON_OVERLAPPED_FOLLOWED_BY

Description
<seq_expr> #=# <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_INTERSECT

Description
<seq_expr> intersect <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_THROUGHOUT

Description
<expr> throughout <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_WITHIN

Description
<seq_expr> within <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_AT

Description
@(<clock_expr) <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_DISABLE_IFF

Description
disable iff (<expr>) <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_SAMPLED

Description
$sampled(<expr>,<clock_expr>)
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_ROSE

Description
$rose(<expr>,<clock_expr>)
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_FELL

Description
$fell(<expr>,<clock_expr>)
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_STABLE

Description
$stable(<expr>,<clock_expr>)
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_PAST

Description
$past(<expr>,<no_of_ticks>,<clock_expr>)
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_MATCH_ITEM_ASSIGN

Description
(<sequence_expr>, <local_var> = <expression>)
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_SEQ_CONCAT

Description
<seq_expr> ##(cycle_delay_range) <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_UNTIL

Description
<property_expr> until <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_S_UNTIL

Description
<property_expr> s_until <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_UNTIL_WITH

Description
<property_expr> until_with <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_S_UNTIL_WITH

Description
<property_expr> s_until_with <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_IMPLIES

Description
<property_expr> implies <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_IFF

Description
<property_expr> iff <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_ACCEPT_ON

Description
accept_on (<expr_or_dist>) <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_REJECT_ON

Description
reject_on (<expr_or_dist>) <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_SYNC_ACCEPT_ON

Description
sync_accept_on (<expr_or_dist>) <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

SVA_SYNC_REJECT_ON

Description
sync_reject_on (<expr_or_dist>) <property_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

Ternary SVA Operators (1 Output, 3 Inputs)

SVA_IF

Description
if (expr) <seq_expr> else <seq_expr>
Ports
No Name Type

0

Y

output

1

A

input

2

B

input

3

C

input

Global Clocking

SVA_GLOBAL_CLOCKING_DEF

Description

SVA Global Clocking Definition.

global clocking <clk_expr>; endclocking
Ports
No Name Type

0

A

input

SVA_GLOBAL_CLOCKING_REF

Description

Global clocking reference.

Ports
No Name Type

0

Y

output

SVA_WIDE_SAMPLED

Description
$sampled(<expr>,<clock_expr>)
Ports
No Name Type

0

Y

{output[m]}

1

A0

{input[m]}

2

A1

{input[n]}

SVA_WIDE_STABLE

Description
$stable(<expr>,<clock_expr>)
Ports
No Name Type

0

Y

{output[m]}

1

A0

{input[m]}

2

A1

{input[n]}

Spice-Level Functions

Description

The primitive functions below describe transistor devices. The function names are borrowed from Spice devices (with the same meaning). Of course, all ports are single-bit.

On the API-level, a cell’s function can be queried using the primFuncOf command ($db primFuncOf $cell).

NMOS

Description

NMOS transistor.

The first three ports are drain, gate, and source respectively, the fourth port (bulk) is optional;

Additional ports may be added (e.g. for substrate).

Example
$db load primitive nmos NMOS
$db load port D *
$db load port G *
$db load port S *
$db load port B *
Ports
No Name Type

0

drain

inout

1

gate

input

2

source

inout

3

bulk

input (optional)

…​

…​

input (optional)

PMOS

Description

A PMOS transistor.

The first three ports are drain, gate, and source respectively, the fourth port (bulk) is optional;

Additional ports may be added (e.g. for substrate).

Ports
No Name Type

0

drain

inout

1

gate

input

2

source

inout

3

bulk

input (optional)

…​

…​

input (optional)

NPN

Description

A bipolar NPN transistor.

The first three ports are collector, base, and emitter respectively, the fourth port (substrate) is optional;

Additional ports may be added.

Example
$db load primitive npn NPN
$db load port C *
$db load port B *
$db load port E *
Ports
No Name Type

0

collector

inout

1

base

input

2

emitter

inout

3

substrate

input (optional)

…​

…​

input (optional)

PNP

Description

A bipolar PNP transistor.

The first three ports are collector, base, and emitter respectively, the fourth port (substrate) is optional;

Additional ports may be added.

Example
$db load primitive pnp PNP
$db load port C *
$db load port B *
$db load port E *
Ports
No Name Type

0

collector

inout

1

base

input

2

emitter

inout

3

substrate

input (optional)

…​

…​

input (optional)

NMOSM

Description

NMOS transistor with multiple gates.

The first three ports are drain, gate, and source respectively, the other optional ports are gates or bulk;

Additional ports may be added (e.g. for substrate).

Example
$db load primitive nmos NMOSM
$db load port D *
$db load port G *
$db load port S *
$db load port G2 * -flag multigate
$db load port B *
Ports
No Name Type

0

drain

inout

1

gate

input

2

source

inout

3

gate2

input (optional)

…​

…​

input (optional)

PMOSM

Description

A PMOS transistor with multiple gates.

The first three ports are drain, gate, and source respectively, the other optional ports are gates or bulk; the fourth port (bulk) is optional;

Additional ports may be added (e.g. for substrate).

Ports
No Name Type

0

drain

inout

1

gate

input

2

source

inout

3

bulk

input (optional)

…​

…​

input (optional)

NPNM

Description

A bipolar NPN transistor with optional bases.

The first three ports are collector, base, and emitter respectively, the other optional ports are bases or bulk;

Additional ports may be added.

Example
$db load primitive npn NPNM
$db load port C *
$db load port B *
$db load port E *
$db load port B2 * -flag multigate
Ports
No Name Type

0

collector

inout

1

base

input

2

emitter

inout

3

base2

input (optional)

…​

…​

input (optional)

PNPM

Description

A bipolar PNP transistor with multiple bases.

The first three ports are collector, base, and emitter respectively, the other optional ports are bases or bulk;

Additional ports may be added.

Example
$db load primitive pnp PNPM
$db load port C *
$db load port B *
$db load port E *
$db load port B2 * -flag multigate
Ports
No Name Type

0

collector

inout

1

base

input

2

emitter

inout

3

base2

input (optional)

…​

…​

input (optional)

RES

Description

A resistor.

Two inout (bidirectional) ports, the third port (bulk) is optional;

Additional ports may be added (e.g. for substrate).

Example
$db load primitive res RES
$db load port a *
$db load port b *
Ports
No Name Type

0

p1

inout

1

p2

inout

2

bulk

input (optional)

…​

…​

input (optional)

CAP

Description

A capacitor.

Two inout (bidirectional) ports, the third port (bulk) is optional;

Additional ports may be added (e.g. for substrate).

Example
$db load primitive cap CAP
$db load port a *
$db load port b *
Ports
No Name Type

0

p1

inout

1

p2

inout

2

bulk

input (optional)

…​

…​

input (optional)

INDUCTOR

Description

An inductor.

Two inout (bidirectional) ports, the third port (bulk) is optional;

Additional ports may be added (e.g. for substrate).

Example
$db load primitive ind INDUCTOR
$db load port a *
$db load port b *
Ports
No Name Type

0

p1

inout

1

p2

inout

2

bulk

input (optional)

…​

…​

input (optional)

DIODE

Description

A diode.

The first port is the anode, the second port is the cathode, the optional third port is bulk;

Additional ports may be added (e.g. for substrate).

Example
$db load primitive diode DIODE
$db load port anode *
$db load port catho *
Ports
No Name Type

0

anode

inout

1

cathode

inout

2

bulk

input (optional)

…​

…​

input (optional)

ZDIODE

Description

A Zener diode.

The first port is the anode, the second port is the cathode, the optional third port is bulk;

Additional ports may be added (e.g. for substrate).

Example
$db load primitive zdiode ZDIODE
$db load port anode *
$db load port catho *
Ports
No Name Type

0

anode

inout

1

cathode

inout

2

bulk

input (optional)

…​

…​

input (optional)

SWITCH

Description

A (controlled) switch.

Two inout (bidirectional) ports, the optional third and fourth ports are used as control inputs.

Example
$db load primitive switch SWITCH
$db load port a *
$db load port b *
$db load port c1 *
$db load port c2 *
Ports
No Name Type

0

p1

inout

1

p2

inout

2

Ctrl+

input (optional)

3

Ctrl-

input (optional)

VSOURCE

Description

A voltage source.

The primitive has either two ports (+, -) or four (+, -, ctrl+, ctrl-). If there are only two ports it is a "normal" voltage source, if there are four ports it’s a "voltage controlled" voltage source — in this case the additional two ports are the control inputs.

Example
$db load primitive vsrc VSOURCE
$db load port + *
$db load port - *
Ports
No Name Type

0

+

inout

1

-

inout

2

Ctrl+

input (optional)

3

Ctrl-

input (optional)

ISOURCE

Description

A current source.

The primitive has either two ports (+, -) or four (+, -, ctrl+, ctrl-). If there are only two ports it is a "normal" current source, if there are four ports it’s a "voltage controlled" current source — in this case the additional two ports are the control inputs.

Example
$db load primitive isrc ISOURCE
$db load port + *
$db load port - *
$db load port c+ *
$db load port c- *
Ports
No Name Type

0

+

inout

1

-

inout

2

Ctrl+

input (optional)

3

Ctrl-

input (optional)

TRANSLINE

Description

A transmission line.

The primitive has 2*n ports; the first n ports are on the one side of the transmission line, the second n ports are on the other side.

Example
$db load primitive transline TRANSLINE
$db load port a0 *
$db load port a1 *
$db load port a2 *
$db load port b0 *
$db load port b1 *
$db load port b2 *
Ports
No Name Type

0

in0

inout

1

in1

inout

…​

…​

…​

(n-1)

in(n-1)

inout

n

out0

inout

n+1

out1

inout

…​

…​

…​

2*n-1

out(n-1)

inout

UDRCLINE

Description

An UDRC line.

The first two ports are the actual line, the third port is ground.

Example
$db load primitive udrcline UDRCLINE
$db load port a *
$db load port b *
$db load port g *
Ports
No Name Type

0

in

inout

1

out

inout

2

ground

inout

AMP

Description

An operational amplifier.

This primitive comes with 3, 5, or 7 ports.

In the 3-port version, only the positive input (+), negative input (-), and output (out) are present.

In the 5-port version, only the positive input (+), negative input (-), output (out), vcc, and vee are present.

In the 7-port version, all ports are present — including the two compensation ports comp1 and comp2.

Example
$db load primitive amp AMP
$db load port - *
$db load port + *
$db load port out *
$db load port vcc *
$db load port vee *
Ports
No Name Type

0

-

input

1

+

input

2

out

output

3

comp1

inout (only in the 7-port version)

4

comp2

inout (only in the 7-port version)

5

vcc

input (only in the 5- and 7-port versions)

6

vee

input (only in the 5- and 7-port versions)

JOSEPHSON_JUNCTION

Description

A Josephson Junction.

This primitive requires 2 ports.

Example
$db load primitive jj JOSEPHSON_JUNCTION
$db load port n1 *
$db load port n2 *
Ports
No Name Type

0

n1

inout

1

n2

inout

UNKNOWNDEV

Description

An unknown device.

This primitive is expected to have at least two inout (bidirectional) ports.

Additional input ports may be added (e.g. for substrate).

Ports
No Name Type

0

p1

inout

1

p2

inout

…​

…​

input (optional)