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112 | ###############################################################
# Generated by: Human Intelligence 2.0
# OS: Linux x86_64(Host ID www.concept.de)
# Generated on: Tue Oct 26 11:26:12 2021
# Design: gl85
# Command: make report_timing
###############################################################
Path 1: VIOLATED (-0.226 ns) Hold Check with Pin CLK
Group: clk
Startpoint: (R) CLK
Clock: (R) clk
Endpoint: (F) WRBAR
Clock: (R) clk
Capture Launch
Clock Edge:+ 0.000 0.000
Src Latency:+ 0.000 0.000
Net Latency:+ 0.000 (I) 0.000 (I)
Arrival:= 0.000 0.000
Hold:+ 0.617
Uncertainty:+ 0.040
Required Time:= 0.657
Launch Clock:= 0.000
Data Path:+ 0.431
Slack:= -0.226
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# Cell Arc Edge Delay Arrival Load Trans Fanout Pin
# (ns) (ns) (pf) (ns)
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
(arrival) CLK R 0.000 0.000 11.034 0.000 7 CLK
AND2 A->O R 0.420 0.420 0.231 0.002 8 IR/B8/U8/O
DFF - R 0.011 0.431 0.001 0.000 1 IR/B8/R0/CK
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Path 2: VIOLATED (-0.044) Hold Check with Pin C2/M0/DFFA/Q
Group: clk
Startpoint: (R) C2/M0/DFFA/Q
Clock: (R) clk
Endpoint: (F) AL/FG_U/U13/CK
Clock: (R) clk
Capture Launch
Clock Edge:+ 0.000 0.000
Src Latency:+ 0.000 0.000
Net Latency:+ 0.000 (I) 0.000 (I)
Arrival:= 0.000 0.000
Hold:+ 0.063
Uncertainty:+ 0.040
Required Time:= 0.103
Launch Clock:= 0.000
Data Path:+ 0.059
Slack:= -0.044
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# Cell Arc Edge Delay Arrival Load Trans Fanout Pin
# (ns) (ns) (pf) (ns)
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
(arrival) CK->Q R 0.000 0.000 11.034 0.000 7 C2/M0/DFFA/Q
INV I->O R 0.008 0.008 0.001 0.002 5 C2/M0/INVA/O
OR3 A->O R 0.010 0.018 0.004 0.004 2 C2/M0/NAND0/O
BUF I->O R 0.010 0.028 0.004 0.002 5 C2/BUF4/O
NOR2 A->O R 0.005 0.033 0.003 0.002 1 AL/FG_U/V29/O
OR2 A->O R 0.001 0.034 0.001 0.002 1 AL/FG_U/V31/O
AND2 A->O R 0.002 0.036 0.003 0.002 1 AL/FG_U/V32/O
OR3 C->O R 0.010 0.046 0.001 0.004 2 AL/FG_U/V25/O
OR2 A->O R 0.001 0.047 0.001 0.002 1 AL/FG_U/V28/O
AND2 A->O R 0.002 0.049 0.002 0.002 1 AL/FG_U/U8/O
DFF - R 0.010 0.059 0.001 0.002 1 AL/FG_U/U13/CK
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Path 3: MET (+0.014) Hold Check with Pin C2/M0/DFFA/Q
Group: clk
Startpoint: (R) C2/M0/DFFA/Q
Clock: (R) clk
Endpoint: (F) AL/FG_U/U13/CK
Clock: (R) clk
Capture Launch
Clock Edge:+ 0.000 0.000
Src Latency:+ 0.000 0.000
Net Latency:+ 0.000 (I) 0.000 (I)
Arrival:= 0.000 0.000
Hold:+ 0.013
Uncertainty:+ 0.040
Required Time:= 0.053
Launch Clock:= 0.000
Data Path:+ 0.067
Slack:= +0.014
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# Cell Arc Edge Delay Arrival Load Trans Fanout Pin
# (ns) (ns) (pf) (ns)
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
(arrival) CLK R 0.000 0.000 11.034 0.000 114 CLK
NOR3 C->O R 0.010 0.010 0.004 0.004 1 IR/NR/O
AND2 B->O R 0.010 0.020 0.004 0.002 8 IR/B8/U8/O
NOR2 CK->Q R 0.005 0.025 0.003 0.002 1 IR/B8/R3/Q
BUF I->O R 0.001 0.026 0.001 0.002 2 IR/B8/U9/BUF4/O
BUF I->O R 0.002 0.028 0.003 0.002 4 IR/BUF4/O
INV I->O R 0.002 0.030 0.003 0.002 2 RGC/RC1/U0/U0/O
AND2 A->O R 0.003 0.033 0.002 0.001 11 RGC/RC1/U0/U2/O
AND2 A->O R 0.002 0.035 0.003 0.002 1 RGC/RC1/U52/O
OR2 B->O R 0.004 0.039 0.004 0.002 1 RGC/RC1/U106/O
OR2 A->O R 0.003 0.042 0.003 0.001 1 RGC/RC1/W2/O
OR2 A->O R 0.002 0.044 0.003 0.002 8 RPD/BC/U2/O
INV I->O R 0.010 0.054 0.001 0.004 1 RPD/BC/U0/U20/G5/O
AND2 A->O R 0.001 0.055 0.001 0.002 1 RPD/BC/U0/U20/G2/O
OR2 A->O R 0.002 0.057 0.002 0.002 1 RPD/BC/U0/U20/G1/O
DFF - R 0.010 0.067 0.001 0.002 1 RPD/BC/U0/R0/D
#-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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