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1076 | ###############################################################################
# Copyright (c) 2008-2024 by Altair Engineering, Inc.
# All rights reserved.
#
# Altair Engineering, Inc. makes this software available as part of the Vision
# tool platform. As long as you are a licensee of the Vision tool platform
# you may make copies of the software and modify it to be used within the
# Vision tool platform, but you must include all of this notice on any copy.
# Redistribution without written permission to any third party, with or
# without modification, is not permitted.
# Altair Engineering, Inc. does not warrant that this software is error free
# or fit for any purpose. Altair Engineering, Inc. disclaims any liability for
# all claims, expenses, losses, damages and costs any user may incur as a
# result of using, copying or modifying the software.
# =============================================================================
# @plugin
# FPGA Symbols
# @namespace
# FPGASymbols
# @section
# Miscellaneous Userware Examples
# @description
# Create nice symbol shapes for all LUT cells.
# @non-interactive
# @files
# cust9/fpga-symbols.tcl
# @example
# demo/edif/pulpino.edf
# @cmdline
# -edif @example[0]
# -userware @files[0]
# @tag
# netlist verilog edif fpga
###############################################################################
# =============================================================================
# Init - Initialize the plugin.
# =============================================================================
#
proc FPGASymbols:Init {} {
global FPGASymbols
set FPGASymbols(callbackRegistered) \
[gui database runOrRegisterChangedCallback FPGASymbols:CreateSymbols]
}
# =============================================================================
# Finit - Finalize the plugin.
# =============================================================================
#
proc FPGASymbols:Finit {} {
global FPGASymbols
if {$FPGASymbols(callbackRegistered)} {
gui database removeChangedCallback FPGASymbols:CreateSymbols
set FPGASymbols(callbackRegistered) 0
}
}
##
# Enable debugging and verbose output.
#
set fpga_symbols_debug 0
# -----------------------------------------------------------------------------
# _DFFports - Return the correct port names for different DFFs.
# -----------------------------------------------------------------------------
#
proc FPGASymbols:_DFFports {name} {
set s "port Q output port D input"
for {set i 0} {$i<[string length $name]} {incr i} {
switch -- [string index $name $i] {
"f" {append s " port C input.clk.neg"}
"r" {append s " port C input.clk"}
"l" {append s " port G input.neg"}
"h" {append s " port G input"}
"R" {append s " port R input.top"}
"S" {append s " port S input.top"}
"E" {append s " port CE input.bot"}
"P" {append s " port PRE input.top"}
"C" {append s " port CLR input.top"}
default {}
}
}
return $s
}
# -----------------------------------------------------------------------------
# _createPrimList - Create a list of valid primitive OIDs based on the given
# nameList.
# The names in the given nameList need to be upper case names.
# -----------------------------------------------------------------------------
#
proc FPGASymbols:_createPrimList {db nameList} {
set primList {}
foreach name $nameList {
catch {
lappend primList [$db oid create "primitive $name $name"]
}
catch {
set name [string tolower $name]
lappend primList [$db oid create "primitive $name $name"]
}
}
foreach prim $primList {
$db flag $prim set red
}
return $primList
}
# =============================================================================
# CreateSymbols - Create nice symbol shapes for all LUT cells.
# =============================================================================
#
proc FPGASymbols:CreateSymbols {db} {
global fpga_symbols_debug FPGASymbols
##
# Return if the database is empty.
#
if {$db == {}} {
return
}
##
# Dump the database before any modifications.
#
if {$fpga_symbols_debug} {
$db dump -sortPins -sortNets -sortPorts -sortSubPorts before
}
if {$FPGASymbols(callbackRegistered)} {
gui database removeChangedCallback FPGASymbols:CreateSymbols
set FPGASymbols(callbackRegistered) 0
}
##
# Truth table to equation mapping (tt2eq).
#
array set _tt2eq {
1:1 !(i0)
1:2 i0
2:1 !(i0+i1)
2:2 i0*!i1
2:4 !i0*i1
2:6 i0^i1
2:7 !(i0*i1)
2:8 i0*i1
2:9 !(i0^i1)
2:B i0+!i1
2:D !i0+i1
2:E i0+i1
3:01 !(i0+i1+i2)
3:02 i0*!i1*!i2
3:04 !i0*i1*!i2
3:07 !((i0*i1)+i2)
3:08 i0*i1*!i2
3:0B (i0+!i1)*!i2
3:0D (!i0+i1)*!i2
3:0E (i0+i1)*!i2
3:10 !i0*!i1*i2
3:13 !((i0*i2)+i1)
3:15 !((i2*i1)+i0)
3:1B !(i0*i2+!i0*i1)
3:1D !(i1*i2+!i1*i0)
3:1F !((i0+i1)*i2)
3:20 i0*!i1*i2
3:23 (i0+!i2)*!i1
3:27 !(i0*i1+!i0*i2)
3:2A (!i2+!i1)*i0
3:2F (i0*!i1)+!i2
3:31 (!i0+i2)*!i1
3:32 (i0+i2)*!i1
3:35 !(i2*i1+!i2*i0)
3:37 !((i0+i2)*i1)
3:3B !((!i0+i2)*i1)
3:40 !i0*i1*i2
3:45 (!i2+i1)*!i0
3:47 !(i1*i0+!i1*i2)
3:4C (!i0+!i2)*i1
3:4F !((i0+!i1)*i2)
3:51 (i2+!i1)*!i0
3:53 !(i2*i0+!i2*i1)
3:54 (i2+i1)*!i0
3:57 !((i2+i1)*i0)
3:5D !((i2+!i1)*i0)
3:69 !(i0^i1^i2)
3:70 (!i0+!i1)*i2
3:73 !((i0+!i2)*i1)
3:75 !((!i2+i1)*i0)
3:7F !(i0*i1*i2)
3:80 i0*i1*i2
3:8A (!i2+i1)*i0
3:8C (i0+!i2)*i1
3:8F (i0*i1)+!i2
3:96 i0^i1^i2
3:A2 (i2+!i1)*i0
3:A8 (i2+i1)*i0
3:AB (!i2*!i1)+i0
3:AC i2*i0+!i2*i1
3:AE (!i2*i1)+i0
3:B0 (i0+!i1)*i2
3:B3 (i0*i2)+!i1
3:B8 i1*i0+!i1*i2
3:BA (i2*!i1)+i0
3:BF i0+!i1+!i2
3:C4 (!i0+i2)*i1
3:C8 (i0+i2)*i1
3:CA i2*i1+!i2*i0
3:CD (!i0*!i2)+i1
3:CE (i0*!i2)+i1
3:D0 (!i0+i1)*i2
3:D5 (i2*i1)+!i0
3:D8 i0*i1+!i0*i2
3:DC (!i0*i2)+i1
3:DF !i0+i1+!i2
3:E0 (i0+i1)*i2
3:E2 i1*i2+!i1*i0
3:E4 i0*i2+!i0*i1
3:EA (i2*i1)+i0
3:EC (i0*i2)+i1
3:EF i0+i1+!i2
3:F1 (!i0*!i1)+i2
3:F2 (i0*!i1)+i2
3:F4 (!i0*i1)+i2
3:F7 !i0+!i1+i2
3:F8 (i0*i1)+i2
3:FB i0+!i1+i2
3:FD !i0+i1+i2
3:FE i0+i1+i2
4:0001 !(i0+i1+i2+i3)
4:0002 i0*!i1*!i2*!i3
4:0004 !i0*i1*!i2*!i3
4:0007 !((i0*i1)+i2+i3)
4:0008 i0*i1*!i2*!i3
4:000B !((!i0*i1)+i2+i3)
4:000D !((i0*!i1)+i2+i3)
4:000E (i0+i1)*!i2*!i3
4:0010 !i0*!i1*i2*!i3
4:0013 !((i0*i2)+i1+i3)
4:0015 !((i1*i2)+i0+i3)
4:0020 i0*!i1*i2*!i3
4:0023 !((!i0*i2)+i1+i3)
4:002A !((i1*i2)+!i0+i3)
4:0031 !((i0*!i2)+i1+i3)
4:0032 (i0+i2)*!i1*!i3
4:0040 !i0*i1*i2*!i3
4:0045 !((!i1*i2)+i0+i3)
4:004C !((i0*i2)+!i1+i3)
4:0051 !((i1*!i2)+i0+i3)
4:0054 (i1+i2)*!i0*!i3
4:0070 !((i0*i1)+!i2+i3)
4:007F !((i0*i1*i2)+i3)
4:0080 i0*i1*i2*!i3
4:008A (i1+!i2)*i0*!i3
4:008C (i0+!i2)*i1*!i3
4:00A2 (!i1+i2)*i0*!i3
4:00A8 (i1+i2)*i0*!i3
4:00B0 (i0+!i1)*i2*!i3
4:00BF !((!i0*i1*i2)+i3)
4:00C4 (!i0+i2)*i1*!i3
4:00C8 (i0+i2)*i1*!i3
4:00D0 (!i0+i1)*i2*!i3
4:00DF !((i0*!i1*i2)+i3)
4:00E0 (i0+i1)*i2*!i3
4:00EF (i0+i1+!i2)*!i3
4:00F7 !((i0*i1*!i2)+i3)
4:00FB (i0+!i1+i2)*!i3
4:00FD (!i0+i1+i2)*!i3
4:00FE (i0+i1+i2)*!i3
4:0100 !(i0+i1+i2+!i3)
4:0103 !((i0*i3)+i1+i2)
4:0105 !((i1*i3)+i0+i2)
4:0111 !((i2*i3)+i0+i1)
4:01FF !((i0+i1+i2)*i3)
4:0200 i0*!i1*!i2*i3
4:0203 !((!i0*i3)+i1+i2)
4:020A !((i1*i3)+!i0+i2)
4:0222 !((i2*i3)+!i0+i1)
4:02FF !((!i0+i1+i2)*i3)
4:0301 !((i0*!i3)+i1+i2)
4:0302 (i0+i3)*!i1*!i2
4:0357 !((i0+i3)*(i1+i2))
4:03AB !((!i0+i3)*(i1+i2))
4:0400 !i0*i1*!i2*i3
4:0405 !((!i1*i3)+i0+i2)
4:040C !((i0*i3)+!i1+i2)
4:0444 !((i2*i3)+i0+!i1)
4:04FF !((i0+!i1+i2)*i3)
4:0501 !((i1*!i3)+i0+i2)
4:0504 (i1+i3)*!i0*!i2
4:0537 !((i0+i2)*(i1+i3))
4:05CD !((i0+i2)*(!i1+i3))
4:0700 !((i0*i1)+i2+!i3)
4:070F !((i0*i1*i3)+i2)
4:0777 !((i0*i1)+(i2*i3))
4:0800 i0*i1*!i2*i3
4:080A (i1+!i3)*i0*!i2
4:080C (i0+!i3)*i1*!i2
4:0888 (!i2+!i3)*i0*i1
4:08FF (i0*i1*!i2)+!i3
4:0A02 (!i1+i3)*i0*!i2
4:0A08 (i1+i3)*i0*!i2
4:0A3B !((!i0+i2)*(i1+i3))
4:0ACE (i0*!i2)+(i1*!i3)
4:0B00 (i0+!i1)*!i2*i3
4:0B0F (i0+!i1+!i3)*!i2
4:0BBB (i0+!i1)*(!i2+!i3)
4:0C04 (!i0+i3)*i1*!i2
4:0C08 (i0+i3)*i1*!i2
4:0C5D !((i0+i3)*(!i1+i2))
4:0CAE (i0*!i3)+(i1*!i2)
4:0D00 (!i0+i1)*!i2*i3
4:0D0F (!i0+i1+!i3)*!i2
4:0DDD (!i0+i1)*(!i2+!i3)
4:0E00 (i0+i1)*!i2*i3
4:0E0F (i0+i1+!i3)*!i2
4:0EEE (i0+i1)*(!i2+!i3)
4:0F07 (!i0+!i1+i3)*!i2
4:0F0B (i0+!i1+i3)*!i2
4:0F0D (!i0+i1+i3)*!i2
4:0F0E (i0+i1+i3)*!i2
4:0F1F !((i0+i1+i3)*i2)
4:0F2F !((!i0+i1+i3)*i2)
4:0F4F !((i0+!i1+i3)*i2)
4:0F8F (i0*i1*!i3)+!i2
4:1000 !i0*!i1*i2*i3
4:1011 !((!i2*i3)+i0+i1)
4:1030 !((i0*i3)+i1+!i2)
4:1050 !((i1*i3)+i0+!i2)
4:10FF !((i0+i1+!i2)*i3)
4:1101 !((i2*!i3)+i0+i1)
4:1110 (i2+i3)*!i0*!i1
4:111F !((i0+i1)*(i2+i3))
4:11F1 !((i0+i1)*(!i2+i3))
4:123A ((i2*!(i1)*!(i0))+((((!(i3)+!(i2))*!(i1))+(!(i3)*!(i2)))*i0))
4:1300 !((i0*i2)+i1+!i3)
4:1333 !((i0*i2*i3)+i1)
4:135F !((i0*i2)+(i1*i3))
4:1500 !((i1*i2)+i0+!i3)
4:153F !((i0*i3)+(i1*i2))
4:1555 !((i1*i2*i3)+i0)
4:1F0F !((i0+i1+!i3)*i2)
4:1F11 !((i0+i1)*(i2+!i3))
4:1FFF !((i0+i1)*i2*i3)
4:2000 i0*!i1*i2*i3
4:2022 (i2+!i3)*i0*!i1
4:2030 (i0+!i3)*!i1*i2
4:20A0 (!i1+!i3)*i0*i2
4:20FF !((!i0+i1+!i2)*i3)
4:2202 (!i2+i3)*i0*!i1
4:2220 (i2+i3)*i0*!i1
4:222F !((!i0+i1)*(i2+i3))
4:22F2 (i0*!i1)+(i2*!i3)
4:2EE2 (((i2^i3)+!(i1))*i0)+((i2^i3)*i1)
4:2300 (i0+!i2)*!i1*i3
4:2333 !((!i0*i2*i3)+i1)
4:23AF !((!i0*i2)+(i1*i3))
4:2A00 (!i1+!i2)*i0*i3
4:2A3F !((!i0*i3)+(i1*i2))
4:2AAA (!i1+!i2+!i3)*i0
4:2F0F (i0*!i1*i3)+!i2
4:2F22 (i0*!i1)+(!i2*i3)
4:2FFF !((!i0+i1)*i2*i3)
4:3010 (!i0+i3)*!i1*i2
4:3020 (i0+i3)*!i1*i2
4:3075 !((i0+i3)*(i1+!i2))
4:30BA (i0*!i3)+(!i1*i2)
4:3100 (!i0+i2)*!i1*i3
4:3133 !((i0*!i2*i3)+i1)
4:31F5 !((i0*!i2)+(i1*i3))
4:3200 (i0+i2)*!i1*i3
4:3233 (i0+i2+!i3)*!i1
4:32FA (i0+i2)*(!i1+!i3)
4:3313 !((i0*i2*!i3)+i1)
4:3323 (i0+!i2+i3)*!i1
4:3331 (!i0+i2+i3)*!i1
4:3332 (i0+i2+i3)*!i1
4:3337 !((i0+i2+i3)*i1)
4:333B !((!i0+i2+i3)*i1)
4:3373 !((i0+!i2+i3)*i1)
4:33B3 (i0*i2*!i3)+!i1
4:3705 !((i0+i2)*(i1+!i3))
4:3733 !((i0+i2+!i3)*i1)
4:37FF !((i0+i2)*i1*i3)
4:3B0A (i0*!i2)+(!i1*i3)
4:3B33 (i0*!i2*i3)+!i1
4:3BFF !((!i0+i2)*i1*i3)
4:3F15 !((i0*!i3)+(i1*i2))
4:3F2A (i0+i3)*(!i1+!i2)
4:3F7F !((i0+i3)*i1*i2)
4:3FBF !((!i0+i3)*i1*i2)
4:4000 !i0*i1*i2*i3
4:4044 (i2+!i3)*!i0*i1
4:4050 (i1+!i3)*!i0*i2
4:40C0 (!i0+!i3)*i1*i2
4:40FF (!i0*i1*i2)+!i3
4:4404 (!i2+i3)*!i0*i1
4:4440 (i2+i3)*!i0*i1
4:4447 ((((!(i3)*!(i2))+i1)*!(i0))+(!(i3)*!(i2)*!(i1)))
4:444F !((i0+!i1)*(i2+i3))
4:44F4 (!i0*i1)+(i2*!i3)
4:4500 (i1+!i2)*!i0*i3
4:4555 !((!i1*i2*i3)+i0)
4:45CF !((i0*i3)+(!i1*i2))
4:4C00 (!i0+!i2)*i1*i3
4:4C5F !((i0*i2)+(!i1*i3))
4:4CCC (!i0+!i2+!i3)*i1
4:4F0F (!i0*i1*i3)+!i2
4:4F44 (!i0*i1)+(!i2*i3)
4:4FFF !((i0+!i1)*i2*i3)
4:5010 (!i1+i3)*!i0*i2
4:5040 (i1+i3)*!i0*i2
4:5073 !((i0+!i2)*(i1+i3))
4:50D8 ((i2*!(i0))+(!(i3)*i1*i0))
4:50DC (!i0*i2)+(i1*!i3)
4:5100 (!i1+i2)*!i0*i3
4:5155 !((i1*!i2*i3)+i0)
4:51F3 !((i0*i3)+(i1*!i2))
4:5400 (i1+i2)*!i0*i3
4:5455 (i1+i2+!i3)*!i0
4:54FC (!i0+!i3)*(i1+i2)
4:5515 !((i1*i2*!i3)+i0)
4:5545 (i1+!i2+i3)*!i0
4:5551 (!i1+i2+i3)*!i0
4:5554 (i1+i2+i3)*!i0
4:5557 !((i1+i2+i3)*i0)
4:555D !((!i1+i2+i3)*i0)
4:5575 !((i1+!i2+i3)*i0)
4:55D5 (i1*i2*!i3)+!i0
4:5703 !((i0+!i3)*(i1+i2))
4:5755 !((i1+i2+!i3)*i0)
4:57FF !((i1+i2)*i0*i3)
4:5D0C (!i0*i3)+(i1*!i2)
4:5D55 (i1*!i2*i3)+!i0
4:5DFF !((!i1+i2)*i0*i3)
4:5F13 !((i0*i2)+(i1*!i3))
4:5F4C (!i0+!i2)*(i1+i3)
4:5F7F !((i1+i3)*i0*i2)
4:5FDF !((!i1+i3)*i0*i2)
4:6996 i0^i1^i2^i3
4:7000 (!i0+!i1)*i2*i3
4:7077 !((i0*i1)+(!i2*i3))
4:70F0 !((i0*i1*i3)+!i2)
4:7333 (!i0*i2*i3)+!i1
4:7350 (!i0*i2)+(!i1*i3)
4:73FF !((i0+!i2)*i1*i3)
4:7530 (!i0*i3)+(!i1*i2)
4:7555 !((i1+!i2+!i3)*i0)
4:75FF !((i1+!i2)*i0*i3)
4:7707 !((i0*i1)+(i2*!i3))
4:7751 (((i3+i2+!(i1))*!(i0))+(i3*!(i1)))
4:7770 (!i0+!i1)*(i2+i3)
4:777F !((i2+i3)*i0*i1)
4:77F7 !((!i2+i3)*i0*i1)
4:7F00 (!i0+!i1+!i2)*i3
4:7F3F !((i0+!i3)*i1*i2)
4:7F5F !((i1+!i3)*i0*i2)
4:7F77 !((i2+!i3)*i0*i1)
4:7FFF !(i0*i1*i2*i3)
4:8000 i0*i1*i2*i3
4:8088 (i2+!i3)*i0*i1
4:80A0 (i1+!i3)*i0*i2
4:80C0 (i0+!i3)*i1*i2
4:80FF (i0*i1*i2)+!i3
4:8808 (!i2+i3)*i0*i1
4:8880 (i2+i3)*i0*i1
4:888F (i0*i1)+(!i2*!i3)
4:88F8 (i0*i1)+(i2*!i3)
4:8A00 (i1+!i2)*i0*i3
4:8AA8 (((i2^i3)+i1)*i0)
4:8AAA (i1+!i2+!i3)*i0
4:8ACF (i0+!i3)*(i1+!i2)
4:8C00 (i0+!i2)*i1*i3
4:8C80 (((i3+i2)*i1*i0)+(i3*!(i2)*i1))
4:8CAF (i0+!i2)*(i1+!i3)
4:8CCC (i0+!i2+!i3)*i1
4:8F0F (i0*i1*i3)+!i2
4:8F88 (i0*i1)+(!i2*i3)
4:8FFF (i0*i1)+!i2+!i3
4:9009 !(i2^i3)*!(i0^i1)
4:9669 !(i0^i1^i2^i3)
4:A020 (!i1+i3)*i0*i2
4:A080 (i1+i3)*i0*i2
4:A0B3 (i0*i2)+(!i1*!i3)
4:A0EC (i0*i2)+(i1*!i3)
4:A200 (!i1+i2)*i0*i3
4:A2AA (!i1+i2+!i3)*i0
4:A2F3 (i0+!i3)*(!i1+i2)
4:A800 (i1+i2)*i0*i3
4:A8AA (i1+i2+!i3)*i0
4:A8FC (i0+!i3)*(i1+i2)
4:AA2A (!i1+!i2+i3)*i0
4:AA8A (i1+!i2+i3)*i0
4:AAA2 (!i1+i2+i3)*i0
4:AAA8 (i1+i2+i3)*i0
4:AAAB !((i1+i2+i3)*!i0)
4:AAAE (i1*!i2*!i3)+i0
4:AABA (!i1*i2*!i3)+i0
4:AAEA (i1*i2*!i3)+i0
4:AB03 (i0*i3)+(!i1*!i2)
4:ABAA (!i1*!i2*i3)+i0
4:ABFF !((i1+i2)*!i0*i3)
4:AE0C (i0*i3)+(i1*!i2)
4:AEAA (i1*!i2*i3)+i0
4:AEFF (i1*!i2)+i0+!i3
4:AF23 (i0+!i2)*(!i1+i3)
4:AF8C (i0+!i2)*(i1+i3)
4:AFBF !((i1+i3)*!i0*i2)
4:AFEF (i1*!i3)+i0+!i2
4:B000 (i0+!i1)*i2*i3
4:B0BB (i0+!i1)*(i2+!i3)
4:B0F0 (i0+!i1+!i3)*i2
4:B333 (i0*i2*i3)+!i1
4:B3A0 (i0*i2)+(!i1*i3)
4:B3FF (i0*i2)+!i1+!i3
4:BA30 (i0*i3)+(!i1*i2)
4:BAAA (!i1*i2*i3)+i0
4:BAFF (!i1*i2)+i0+!i3
4:BB0B (i0+!i1)*(!i2+i3)
4:BBB0 (i0+!i1)*(i2+i3)
4:BBBF !((i2+i3)*!i0*i1)
4:BBFB (i2*!i3)+i0+!i1
4:BF00 (i0+!i1+!i2)*i3
4:BF3F (i0*i3)+!i1+!i2
4:BFAF (!i1*i3)+i0+!i2
4:BFBB (!i2*i3)+i0+!i1
4:BFFF !(!i0*i1*i2*i3)
4:C040 (!i0+i3)*i1*i2
4:C080 (i0+i3)*i1*i2
4:C0D5 (!i0*!i3)+(i1*i2)
4:C0EA (i0*!i3)+(i1*i2)
4:C400 (!i0+i2)*i1*i3
4:C4CC (!i0+i2+!i3)*i1
4:C4F5 (!i0+i2)*(i1+!i3)
4:C800 (i0+i2)*i1*i3
4:C8C0 (((i3+i2)*i1*i0)+(i2*i1))
4:C8CC (i0+i2+!i3)*i1
4:C8FA (i0+i2)*(i1+!i3)
4:CC4C (!i0+!i2+i3)*i1
4:CC8C (i0+!i2+i3)*i1
4:CCC4 (!i0+i2+i3)*i1
4:CCC8 (i0+i2+i3)*i1
4:CCCD !((i0+i2+i3)*!i1)
4:CCCE (i0*!i2*!i3)+i1
4:CCDC (!i0*i2*!i3)+i1
4:CCEC (i0*i2*!i3)+i1
4:CD05 (!i0*!i2)+(i1*i3)
4:CDCC (!i0*!i2*i3)+i1
4:CDFF !((i0+i2)*!i1*i3)
4:CE0A (i0*!i2)+(i1*i3)
4:CECC (i0*!i2*i3)+i1
4:CEFF (i0*!i2)+i1+!i3
4:CF45 (!i0+i3)*(i1+!i2)
4:CF8A (i0+i3)*(i1+!i2)
4:CFDF !((i0+i3)*!i1*i2)
4:CFEF (i0*!i3)+i1+!i2
4:D000 (!i0+i1)*i2*i3
4:D0DD (!i0+i1)*(i2+!i3)
4:D0F0 (!i0+i1+!i3)*i2
4:D555 (i1*i2*i3)+!i0
4:D5C0 (!i0*i3)+(i1*i2)
4:D5FF (i1*i2)+!i0+!i3
4:DC50 (!i0*i2)+(i1*i3)
4:DCCC (!i0*i2*i3)+i1
4:DCFF (!i0*i2)+i1+!i3
4:DD0D (!i0+i1)*(!i2+i3)
4:DDD0 (!i0+i1)*(i2+i3)
4:DDDF !((i2+i3)*i0*!i1)
4:DDFD (i2*!i3)+!i0+i1
4:DF00 (!i0+i1+!i2)*i3
4:DF5F (i1*i3)+!i0+!i2
4:DFCF (!i0*i3)+i1+!i2
4:DFDD (!i2*i3)+!i0+i1
4:DFFF !(i0*!i1*i2*i3)
4:E000 (i0+i1)*i2*i3
4:E0EE (i0+i1)*(i2+!i3)
4:E0F0 (i0+i1+!i3)*i2
4:EAAA (i1*i2*i3)+i0
4:EAC0 (i0*i3)+(i1*i2)
4:EAFF (i1*i2)+i0+!i3
4:ECA0 (i0*i2)+(i1*i3)
4:ECCC (i0*i2*i3)+i1
4:ECFF (i0*i2)+i1+!i3
4:EE0E (i0+i1)*(!i2+i3)
4:EEE0 (i0+i1)*(i2+i3)
4:EEE2 (((i3+i2+!(i1))*i0)+((i3+i2)*i1))
4:EEEF (!i2*!i3)+i0+i1
4:EEFE (i2*!i3)+i0+i1
4:EF00 (i0+i1+!i2)*i3
4:EFAF (i1*i3)+i0+!i2
4:EFCF (i0*i3)+i1+!i2
4:EFE0 (((i3+i2)*(i1+i0))+(i3*!(i2)))
4:EFEE (!i2*i3)+i0+i1
4:EFFF i0+i1+!i2+!i3
4:F070 (!i0+!i1+i3)*i2
4:F0B0 (i0+!i1+i3)*i2
4:F0D0 (!i0+i1+i3)*i2
4:F0E0 (i0+i1+i3)*i2
4:F0F1 !((i0+i1+i3)*!i2)
4:F0F2 (i0*!i1*!i3)+i2
4:F0F4 (!i0*i1*!i3)+i2
4:F0F8 (i0*i1*!i3)+i2
4:F111 (!i0*!i1)+(i2*i3)
4:F1F0 (!i0*!i1*i3)+i2
4:F1FF !((i0+i1)*!i2*i3)
4:F222 (i0*!i1)+(i2*i3)
4:F2F0 (i0*!i1*i3)+i2
4:F2FF (i0*!i1)+i2+!i3
4:F351 (!i0+i3)*(!i1+i2)
4:F3A2 (i0+i3)*(!i1+i2)
4:F3F7 !((i0+i3)*i1*!i2)
4:F3FB (i0*!i3)+!i1+i2
4:F444 (!i0*i1)+(i2*i3)
4:F4F0 (!i0*i1*i3)+i2
4:F4FF (!i0*i1)+i2+!i3
4:F531 (!i0+i2)*(!i1+i3)
4:F5C4 (!i0+i2)*(i1+i3)
4:F5F7 !((i1+i3)*i0*!i2)
4:F5FD (i1*!i3)+!i0+i2
4:F700 (!i0+!i1+i2)*i3
4:F777 (i2*i3)+!i0+!i1
4:F7F3 (!i0*i3)+!i1+i2
4:F7F5 (!i1*i3)+!i0+i2
4:F7FF !i0+!i1+i2+!i3
4:F888 (i0*i1)+(i2*i3)
4:F8F0 (i0*i1*i3)+i2
4:F8FF (i0*i1)+i2+!i3
4:FA32 (i0+i2)*(!i1+i3)
4:FAC8 (i0+i2)*(i1+i3)
4:FAFB (!i1*!i3)+i0+i2
4:FAFE (i1*!i3)+i0+i2
4:FB00 (i0+!i1+i2)*i3
4:FBBB (i2*i3)+i0+!i1
4:FBF3 (i0*i3)+!i1+i2
4:FBFA (!i1*i3)+i0+i2
4:FBFF i0+!i1+i2+!i3
4:FC54 (!i0+i3)*(i1+i2)
4:FC74 (((i2+i1)*!(i0))+(i2*!(i1))+(i3*i1))
4:FCA8 (i0+i3)*(i1+i2)
4:FCFD (!i0*!i3)+i1+i2
4:FCFE (i0*!i3)+i1+i2
4:FD00 (!i0+i1+i2)*i3
4:FDDD (i2*i3)+!i0+i1
4:FDF5 (i1*i3)+!i0+i2
4:FDFC (!i0*i3)+i1+i2
4:FDFF !i0+i1+i2+!i3
4:FE00 (i0+i1+i2)*i3
4:FEEE (i2*i3)+i0+i1
4:FEFA (i1*i3)+i0+i2
4:FEFC (i0*i3)+i1+i2
4:FEFF i0+i1+i2+!i3
4:FF01 (!i0*!i1*!i2)+i3
4:FF02 (i0*!i1*!i2)+i3
4:FF04 (!i0*i1*!i2)+i3
4:FF08 (i0*i1*!i2)+i3
4:FF10 (!i0*!i1*i2)+i3
4:FF1F !((i0+i1)*i2*!i3)
4:FF20 (i0*!i1*i2)+i3
4:FF2F (i0*!i1)+!i2+i3
4:FF37 !((i0+i2)*i1*!i3)
4:FF3B (i0*!i2)+!i1+i3
4:FF40 (!i0*i1*i2)+i3
4:FF4F (!i0*i1)+!i2+i3
4:FF57 !((i1+i2)*i0*!i3)
4:FF5D (i1*!i2)+!i0+i3
4:FF73 (!i0*i2)+!i1+i3
4:FF75 (!i1*i2)+!i0+i3
4:FF7F !(i0*i1*i2*!i3)
4:FF80 (i0*i1*i2)+i3
4:FF8F (i0*i1)+!i2+i3
4:FFAB (!i1*!i2)+i0+i3
4:FFAE (i1*!i2)+i0+i3
4:FFB3 (i0*i2)+!i1+i3
4:FFBA (!i1*i2)+i0+i3
4:FFBF i0+!i1+!i2+i3
4:FFCD (!i0*!i2)+i1+i3
4:FFCE (i0*!i2)+i1+i3
4:FFD5 (i1*i2)+!i0+i3
4:FFDC (!i0*i2)+i1+i3
4:FFDF !i0+i1+!i2+i3
4:FFE0 (((i3+i2)*(i1+i0))+i3)
4:FFEA (i1*i2)+i0+i3
4:FFEC (i0*i2)+i1+i3
4:FFEF i0+i1+!i2+i3
4:FFF1 (!i0*!i1)+i2+i3
4:FFF2 (i0*!i1)+i2+i3
4:FFF4 (!i0*i1)+i2+i3
4:FFF7 !i0+!i1+i2+i3
4:FFF8 (i0*i1)+i2+i3
4:FFFB i0+!i1+i2+i3
4:FFFD !i0+i1+i2+i3
4:FFFE i0+i1+i2+i3
}
array unset cell2sym
array set _Vhash {}
##
# Loop over each module.
#
$db foreach module mod {
##
# Loop over each instance in the current module.
#
$db foreach inst $mod inst {
##
# If there is no INIT attribute at this instance then continue.
#
set v [$db attr $inst getValue INIT]
if {$v == ""} {
set v [$db attr $inst getValue init]
continue
}
##
# Get the cell referenced by this instance.
#
set cell [$db down $inst]
set cname [$db oid oname $cell]
##
# Skip all cells except LUTs.
#
if {![string match -nocase "lut*" $cname]} {
continue
}
##
# If this cell is not empty then print an error and continue.
#
if {[$db oid type $cell] == "module"} {
set empty 1
$db foreach inst $cell i {set empty 0; break}
if {!$empty} {
if {$fpga_symbols_debug} {
zmessage print ERR "$cname is not empty, but INIT = $v"
}
continue
}
}
##
# reformat the init value
#
set numBits [string index $cname 3]
set v [regsub {0x} $v {}]
set v [regsub {0X} $v {}]
##
# Add support for values in the form:
# 4'h4
# 16'h0007
#
set idx [string first "'" $v]
if {$idx > 0} {set v [string range $v [incr idx 2] end]}
set v [format "%0[lindex {0 1 1 2 4} $numBits]s" \
[string toupper $v]]
##
# Create a hash table with the cell name as the key. The value
# contains all INIT values of this LUT cell.
# Also create a list of all instances for each INIT value.
#
lappend _Vhash($cname:$v) $inst
if {![info exists cell2sym($cname)]} {set cell2sym($cname) {}}
if {[lsearch $cell2sym($cname) $v] >= 0} {
continue
}
lappend cell2sym($cname) $v
}
}
##
# Initialize variables needed to generate statistics.
#
set dupl 0
set adds 0
set miss 0
##
# Loop over all cells.
#
if {$fpga_symbols_debug} {
set loadToCone {}
}
foreach cname [array names cell2sym] {
##
# Get the number of bits of the LUT
#
set numBits [string index $cname 3]
##
# Loop over all different INIT values of this cell.
#
foreach v $cell2sym($cname) {
if {![info exists _tt2eq($numBits:$v)]} {
if {$fpga_symbols_debug} {
zmessage print ERR \
"No equation for $numBits bit LUT with INIT=$v"
}
incr miss
continue
}
##
# First try to create a module object. If this fails then it
# need to be a primitive.
#
set type "module"
set function ""
if {[catch {set cell [$db oid create "module $cname $cname"]}]} {
set type "primitive"
set function "UNKNOWN"
set cell [$db oid create "primitive $cname $cname"]
}
##
# Map equation to symbol.
#
set equation $_tt2eq($numBits:$v)
##
# Find the name of the output port.
#
set outputName ""
$db foreach oPort output $cell p {set outputName [$db oid oname $p]}
if {$outputName == ""} {
if {$fpga_symbols_debug} {
zmessage print ERR \
"No output port at cell '[$db oid oname $cell]'"
}
continue
}
##
# Create a symbol based on the Boolean equation of this cell.
#
set nlv [gui schem nlv]
set symStr [$nlv symlib map_bool $outputName $equation]
if {($symStr == "") || [string match "BOX*" $symStr]} {
if {$fpga_symbols_debug} {
zmessage print ERR "Cannot map '$equation' => $symStr"
}
incr miss
continue
}
##
# Duplicate the cell.
#
incr dupl
set cmd [list $db load $type ${cname}_$v]
if {$function ne ""} {
lappend cmd $function
}
eval $cmd
##
# Load the ports of the new cell according to the port order in
# the equation.
#
foreach {p name dir} [lrange $symStr 1 end] {
set dir [string map {.top "" .bot "" .left "" .right ""} $dir]
$db load port $name $dir
}
set newcell [$db oid create "$type ${cname}_$v ${cname}_$v"]
incr adds
if {[string range $symStr 0 2] == "MUX"} {
append symStr " text 0=[lindex $symStr 11]\\n1="
append symStr "[lindex $symStr 8] -cc 20 0 10"
}
$db attr $newcell set @symbol=-$symStr
$db attr $newcell set "@nlv=$cname\nINIT=%INIT\n$equation"
$db flag $newcell set red
##
# Change the cellRef of all instances of this cell
# with the same INIT value.
# Also disconnect all nets from the pins and remember the
# connectivity. After changing the cellref reconnect all nets.
#
foreach inst $_Vhash($cname:$v) {
set iName [$db oid oname $inst]
array unset _con
##
# Remember the connectivity and disconnect.
#
$db foreach pin $inst _pin {
if {![$db isConnected $_pin]} {
continue
}
set pName [string tolower [$db oid pname $_pin]]
set _con($pName) [$db oid oname [$db connectedNet $_pin]]
$db oper disconnect $_pin
}
##
# Change referenced cell.
#
$db oper changecellref $inst ${cname}_$v
##
# Reconnect all pins.
#
$db reloadModule [$db oid oname [$db parentModule $inst]]
$db foreach pin $inst _pin {
set pName [string tolower [$db oid pname $_pin]]
set sp [$db search pin $inst $pName]
if {[$db oid isnull $sp]} {
set sp [$db search pin $inst [string tolower $pName]]
}
if {[$db oid isnull $sp]} {
set sp [$db search pin $inst [string toupper $pName]]
}
set sp [$db oid pname $sp]
if {![info exists _con($pName)]} {
continue
}
$db load net $_con($pName) -pin $iName $sp
}
}
if {$fpga_symbols_debug} {
lappend loadToCone [lindex $_Vhash($cname:$v) 0]
}
}
}
##
# Add BUF symbols.
#
foreach prim [FPGASymbols:_createPrimList $db {IBUF OBUF BUF BUFG BUFGP}] {
$db attr $prim set "@symbol=BUF"
if {[string match -nocase "bufg*" [$db oid oname $prim]]} {
$db attr $prim set "@nlv=GLOBAL\nCLOCK BUFFER"
}
incr adds
}
##
# Add INV symbols.
#
foreach prim [FPGASymbols:_createPrimList $db {INV}] {
$db attr $prim set "@symbol=INV"
incr adds
}
##
# Add MUX symbols.
#
set muxPrims {
MUXCY
MUXCY_L
MUXCY_D
MUXF5
MUXF6
MUXF7
MUXF8
MUXF5_L
MUXF6_L
MUXF7_L
MUXF8_L
MUXF5_D
MUXF6_D
MUXF7_D
MUXF8_D
}
foreach prim [FPGASymbols:_createPrimList $db $muxPrims] {
set sym "-MUX port s input.bot"
$db attr $prim set "@symbol=$sym"
incr adds
}
##
# Add XOR symbols.
#
foreach prim [FPGASymbols:_createPrimList $db {XORCY}] {
$db attr $prim set "@symbol=XOR"
incr adds
}
##
# Add AND symbols.
#
foreach prim [FPGASymbols:_createPrimList $db {MULT_AND}] {
$db attr $prim set "@symbol=AND"
incr adds
}
##
# Add BUFIF0/BUFIF1 symbols.
#
foreach prim [FPGASymbols:_createPrimList $db {BUFT}] {
$db attr $prim set "@symbol=BUFIF0"
incr adds
}
foreach prim [FPGASymbols:_createPrimList $db {BUFE}] {
$db attr $prim set "@symbol=BUFIF1"
incr adds
}
##
# Add DFF(GEN) symbols.
#
array set nameToPort {
FD r FDR rR FDS rS FDRS rRS FDSR rSR
FDE rE FDRE rRE FDSE rSE FDRSE rRSE FDSRE rSRE
FDC rC FDP rP FDCP rCP FDCE rCE FDPE rPE
FDCPE rCPE FD_1 f FDR_1 fR FDS_1 fS FDRS_1 fRS
FDSR_1 fSR FDE_1 fE FDRE_1 fRE FDSE_1 fSE FDRSE_1 fRSE
FDSRE_1 fSRE FDC_1 fC FDP_1 fP FDCP_1 fCP FDCE_1 fCE
FDPE_1 fPE FDCPE_1 fCPE LD h LDR hR LDS hS
LDRS hRS LDSR hSR LDE hE LDRE hRE LDSE hSE
LDRSE hRSE LDSRE hSRE LDC hC LDP hP LDCP hCP
LDCE hCE LDPE hPE LDCPE hCPE LD_1 l LDR_1 lR
LDS_1 lS LDRS_1 lRS LDSR_1 lSR LDE_1 lE LDRE_1 lRE
LDSE_1 lSE LDRSE_1 lRSE LDSRE_1 lSRE LDC_1 lC LDP_1 lP
LDCP_1 lCP LDCE_1 lCE LDPE_1 lPE LDCPE_1 lCPE
}
foreach prim [FPGASymbols:_createPrimList $db [array names nameToPort]] {
set pName [string toupper [$db oid oname $prim]]
$db attr $prim set \
"@symbol=-GEN [FPGASymbols:_DFFports $nameToPort($pName)]"
incr adds
}
##
# Update all OIDs with changed cellRef and inform the GUI that the
# database has changed.
#
$db oper changecellref -updateOIDs
gui database changed $db
##
# Generate statistics: add all instances with a new symbol to the Mem
# window and print the statistic to the Console window.
#
if {$fpga_symbols_debug} {
set ic 0
set iList {}
$db foreach top top {
$db flat foreach instOfCell red $top inst {
incr ic
lappend iList $inst
}
}
gui mem append $iList
gui cone load $loadToCone
gui window show Schem
gui window show Cone
set msg "Duplicated $dupl cells and added $adds symbols to $ic "
append msg "instances. Kept $miss LUT symbols."
gui console print $msg
##
# Dump the database after all modifications.
#
$db dump -sortPins -sortNets -sortPorts -sortSubPorts after
}
}
# =============================================================================
# Call the initialization procedure.
# =============================================================================
#
FPGASymbols:Init
|