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188 | ###############################################################################
# Copyright (c) 2011-2024 by Altair Engineering, Inc.
# All rights reserved.
#
# Altair Engineering, Inc. makes this software available as part of the Vision
# tool platform. As long as you are a licensee of the Vision tool platform
# you may make copies of the software and modify it to be used within the
# Vision tool platform, but you must include all of this notice on any copy.
# Redistribution without written permission to any third party, with or
# without modification, is not permitted.
# Altair Engineering, Inc. does not warrant that this software is error free
# or fit for any purpose. Altair Engineering, Inc. disclaims any liability for
# all claims, expenses, losses, damages and costs any user may incur as a
# result of using, copying or modifying the software.
# =============================================================================
# @script
# Quartus utilities.
#
# This file contains a set of utility procedures used by the other
# scripts in this directory.
###############################################################################
# =============================================================================
# TclString - Mask special chars and return a Tcl conform string.
# =============================================================================
#
proc QuUtils:TclString {s} {
return [string map {\[ \\[ \] \\]} $s]
}
# =============================================================================
# WriteLine - Write out a line to the given output file. Mask all special Tcl
# characters.
# =============================================================================
#
proc QuUtils:WriteLine {fileid line} {
puts $fileid [QuUtils:TclString $line]
}
# -----------------------------------------------------------------------------
# _fullPath -
# -----------------------------------------------------------------------------
#
proc QuUtils:_fullPath {base fname} {
if {[file pathtype $fname] == "absolute"} {
return $fname
}
return [file join $base $fname]
}
# =============================================================================
# ReadFileSet - Read Verilog fileset and set global assignments in Quartus.
# =============================================================================
#
proc QuUtils:ReadFileSet {fname {fsrel 0}} {
if {$fsrel} {
set base [file dirname $fname]
} else {
set base . ;# files in a normal fileset are *not* relative to fileset
}
set f [open $fname r]
while {[gets $f line] >= 0} {
set line [string trim $line]
switch -glob -- $line {
{//gv_fsrel} {set base [file dirname $fname]}
{//gv_verilogvers} {
set m VERILOG_2001
switch -- [string range $line 15 end] {
{Verilog 95} {set m VERILOG_1995}
{Verilog 2001} {set m VERILOG_2001}
{SystemVerilog 2005} {set m SYSTEMVERILOG_2005}
default {}
}
set_global_assignment -name VERILOG_INPUT_VERSION $m
}
{//*} continue
{-symlib*} continue
{-f *} {
set fname [string range $line 3 end]
QuUtils:ReadFileSet [QuUtils:_fullPath $base $fname] $fsrel
}
{-v *} {
set fn [string range $line 3 end]
set_global_assignment -name VERILOG_FILE \
[QuUtils:_fullPath $base $fn]
}
{-y *} {
set d [string range $line 3 end]
set_global_assignment -name SEARCH_PATH \
[QuUtils:_fullPath $base $d]
}
{+incdir+*} {
set d [string range $line 8 end]
set_global_assignment -name SEARCH_PATH \
[QuUtils:_fullPath $base $d]
}
{+libext+*} {
set ext [string range $line 8 end]
puts "$$line ignored"
}
{+define+*} {
set def [string range $line 8 end]
set_global_assignment -name VERILOG_MACRO $def
}
default {
set_global_assignment -name VERILOG_FILE \
[QuUtils:_fullPath $base $line]
}
}
}
close $f
}
# =============================================================================
# CreateProject - Create a Verilog project in Quartus
#
# - prjName - name of project
# - topName - name of top entity
# - family - Possible values are (Quartus II 10.0 SP1):
# Stratix, Stratix II, Stratix II GX, Stratix III
# Cyclone, Cyclone II, Cyclone III,
# Cyclone III LS, Cyclone IV E, Cyclone IV GX
# MAX3000A, MAX7000AE, MAX7000B, MAX7000S, MAX II
# Arria GX, Arria II GX
# - files - list of source files (maybe empty, if fileset is
# used)
# - fileset - file name of verilog fileset
# - fsrel - Boolean, if true all relative files in fileset are
# relative to location of fileset.
# =============================================================================
#
proc QuUtils:CreateProject {prjName topName family files fileset fsrel} {
package require ::quartus::project
package require ::quartus::flow
project_new -overwrite $prjName
if {$topName != {}} {
set_global_assignment -name TOP_LEVEL_ENTITY $topName
}
foreach fn $files {
set_global_assignment -name VERILOG_FILE $fn
}
if {$fileset != {}} {
QuUtils:ReadFileSet $fileset $fsrel
}
set_global_assignment -name FAMILY $family
set_global_assignment -name DEVICE auto
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL \
PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FITTER_EFFORT "FAST FIT"
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT ON
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition \
-to | -section_id Top
##
# Commit assignments
#
export_assignments
##
# compile
#
execute_flow -compile
##
# write sdc file
#
create_timing_netlist
write_sdc -expand $prjName.sdc
project_close
}
|