obfuscate/README.adoc

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:source-highlighter: pygments


= VERILOG Obfuscate
Script to mangle all names of Verilog components.

== Overview
* The option `Compact Schematic` must be disabled (`-compact off`).
* Macros may not work properly.
* Unix line endings required (No CRLF).

== What is working
* obfuscation of the name of
        ** modules
        ** ports
        ** instances
        ** wires
        ** register
        ** parameter
        ** defparam
        ** localparam
* Removing of comments (line comment `//` and block comment `/* */`)
* Preserving of pragmas (e.g. `// synopsys synthesis off`)
* White list of ignored words
* Verilog keywords are ignored
* Preserve top level ports names
* (Optional) Whitespace elimination
* (Optional) Deletion of empty lines

== Experimental
* Obfuscation of paths in ``include` statement
* Obfuscation of macro names (``define`)
* Obfuscation of fileset (`+incdir`, `-F`, `-f`, `-v`, `-y`)
* File hierarchy is preserved, but obfuscated
* names of macros defined in fileset (`*.f`)

== What is not working
* Block/label names are not obfuscated
* Output to single file is not supported
* Ignored code blocks after ``ifdef` are not removed
* Code for testbenches
* Escaped identifiers
* Environment variables in filesets
* If an identifier is defined by macro it is not obfuscated without option
obfuscate macros
* SystemVerilog typedef structs

== Nanotime Example
 * Load Aquarius example
        ** `File` > `Open` > `Read RTL` > Folder Symbol > Select Fileset
        `demo/rtl/aquarius/aquarius.f`
        ** Open tab `Options` and deselect `Compact Schematic`
 * Load Obfuscate Userware
        ** `Tools` > `Plugins` > Select `ObfuscateVerilog`
        ** Select `Userware` > `Obfuscate Verilog` and generate obfuscated
        design.
 * Load NanoTime report
        ** `Tools` > `Plugins` > Select `NanoTime`
        ** Select `Userware` > `Load Obfuscated NanoTime`
        ** Select NanoTime report file `demo/api/obfuscate/obfuscatedNanoTimeReport_aquarius.rpt`
        ** Select ObfuscateMap file `ObfuscateMap.tcl` in export directory.

 * Start via cmdline:

== Examples
[source,verilog]