1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50 |
****************************************
Report : timing
-path full
-delay max
-max_paths 200
Design : bus85
Version: 2001.6
Date : Wed Jun 6 15:46:53 2001
****************************************
Operating Conditions: static Library: bus85
Wire Load Model Mode: enclosed
Startpoint: CLK (input port clocked by CLK)
Endpoint: SOD (output port clocked by CLK)
Path Group: CLK
Path Type: max
Point Cap Trans Incr Path
--------------------------------------------------------------------------
clock CLK (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 3.00 3.00 f
CLK (in) 0.00 0.00 3.00 f
IR/CLK (INST_REG) 12.00 0.57 0.00 3.00 f
IR/NR/C (nor3) 3.10 0.23 3.67 6.67 f
IR/B8/WRENABLE (REG8BIT) 2.57 0.56 1.03 7.70 r
IR/B8/U8/B (and2) 3.12 1.30 2.05 9.75 r
IR/B8/R0/CK (DFF) 1.04 2.81 0.00 9.75 r
IR/B8/R0/Q (DFF) 1.45 0.20 0.00 9.75 f
IR/B8/U9/I[7] (BUF8) 1.23 0.30 0.00 9.75 f
IR/B8/U9/BUF7/I (BUF) 0.51 0.40 0.00 9.75 f
IR/B8/U9/BUF7/O (BUF) 0.23 0.50 0.00 9.75 f
IR/B8/U9/O[7] (BUF8) 0.56 0.70 0.00 9.75 f
IR/B8/Q0 (REG8BIT) 1.21 0.61 0.00 9.75 f
IR/B3/B (or2) 2.12 0.21 0.00 9.75 f
IR/ID16 (INST_REG) 1.21 0.12 0.00 9.75 f
SOD (out) 0.18 0.00 33.42 f
data arrival time 33.42
clock CLK (rise edge) 17.50 17.50
clock network delay (ideal) 0.00 17.50
output external delay -3.00 14.50
data required time 14.50
--------------------------------------------------------------------------
data required time 14.50
data arrival time -33.42
--------------------------------------------------------------------------
slack (VIOLATED) -18.92
|