1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424 | ###############################################################################
# Copyright (c) 2004-2024 by Altair Engineering, Inc.
# All rights reserved.
#
# Altair Engineering, Inc. makes this software available as part of the Vision
# tool platform. As long as you are a licensee of the Vision tool platform
# you may make copies of the software and modify it to be used within the
# Vision tool platform, but you must include all of this notice on any copy.
# Redistribution without written permission to any third party, with or
# without modification, is not permitted.
# Altair Engineering, Inc. does not warrant that this software is error free
# or fit for any purpose. Altair Engineering, Inc. disclaims any liability for
# all claims, expenses, losses, damages and costs any user may incur as a
# result of using, copying or modifying the software.
# =============================================================================
# @userware
# Stripped-Down BUS85
# @section
# Load Netlist Data
# @description
# Stripped-down version of bus85.tcl
#
# Stripped down by:
# ```TCL
# $db foreach module m {
# if {[$db refCount $m] == 0} {
# puts $m
# }
# }
# ```
# @files
# oem/alu.tcl
# @tag
# zdb netlist
###############################################################################
# ======================
# create new database
#
set db [zdb new]
# ======================
# load gate-level primitives
#
$db load primitive and5 AND
$db load port O output
$db load port A input
$db load port B input
$db load port C input
$db load port D input
$db load port E input
$db load primitive not1 INV
$db load port O1 output
$db load port I input
$db load primitive xnor2 XNOR
$db load port O output
$db load port A input
$db load port B input
$db load primitive nor3 NOR
$db load port O output
$db load port A input
$db load port B input
$db load port C input
$db load primitive and2 AND
$db load port O output
$db load port A input
$db load port B input
$db load primitive or3 OR
$db load port O output
$db load port A input
$db load port B input
$db load port C input
$db load primitive and4 AND
$db load port O output
$db load port A input
$db load port B input
$db load port C input
$db load port D input
$db load primitive or2 OR
$db load port O output
$db load port A input
$db load port B input
$db load primitive and3 AND
$db load port O output
$db load port A input
$db load port B input
$db load port C input
$db load primitive nand2 NAND
$db load port O output
$db load port A input
$db load port B input
$db load primitive nor2 NOR
$db load port O output
$db load port A input
$db load port B input
$db load primitive or4 OR
$db load port O output
$db load port A input
$db load port B input
$db load port C input
$db load port D input
$db load primitive nor4 NOR
$db load port O output
$db load port A input
$db load port B input
$db load port C input
$db load port D input
$db load primitive nand4 NAND
$db load port O output
$db load port A input
$db load port B input
$db load port C input
$db load port D input
$db load primitive nand5 NAND
$db load port O output
$db load port A input
$db load port B input
$db load port C input
$db load port D input
$db load port E input
$db load primitive DFF DFF
$db load port Q output
$db load port D input
$db load port CK input
$db load port SET input
$db load port CLR input
$db load primitive xor2 XOR
$db load port O output
$db load port A input
$db load port B input
$db load primitive and8 AND
$db load port O output
$db load port A input
$db load port B input
$db load port C input
$db load port D input
$db load port E input
$db load port F input
$db load port G input
$db load port H input
$db load primitive nor8 NOR
$db load port O output
$db load port A input
$db load port B input
$db load port C input
$db load port D input
$db load port E input
$db load port F input
$db load port G input
$db load port H input
# ======================
# define gate-level primitives from spice
# (was converted from bus85prim.sp)
set sfile "[file dirname [info script]]/bus85prim.sp"
#
$db load primitive cmosn NMOS \
-attr level=2 \
-attr vto=0.779 \
-attr kp=3.52e-05 \
-attr gamma=1.04 \
-attr phi=0.6 \
-attr cgso=5.2e-10 \
-attr cgdo=5.2e-10 \
-attr rsh=25 \
-attr cj=0.00042 \
-attr mj=0.5 \
-attr cjsw=9e-10 \
-attr mjsw=0.33 \
-attr tox=5e-08 \
-attr nsub=1e+16 \
-attr nss=0 \
-attr nfs=1.306e+11 \
-attr tpg=1 \
-attr xj=3.85e-08 \
-attr ld=1e-07 \
-attr uo=400 \
-attr ucrit=999000 \
-attr uexp=0.001001 \
-attr vmax=32585.3 \
-attr neff=0.01001 \
-attr delta=1.33 \
-attr "@nlv=W=\$w\nL=\$l" \
-spos $sfile 16 420
$db load port d inout
$db load port g input
$db load port s inout
$db load port b input
$db load primitive cmosp PMOS \
-attr level=2 \
-attr vto=-0.988 \
-attr kp=1.206e-05 \
-attr gamma=0.619 \
-attr phi=0.6 \
-attr cgso=4e-10 \
-attr cgdo=4e-10 \
-attr rsh=95 \
-attr cj=0.00032 \
-attr mj=0.5 \
-attr cjsw=5.5e-10 \
-attr mjsw=0.33 \
-attr tox=5e-08 \
-attr nsub=8.158e+14 \
-attr nss=0 \
-attr nfs=5.55e+09 \
-attr tpg=-1 \
-attr xj=1.46e-07 \
-attr ld=2.52e-07 \
-attr uo=150 \
-attr ucrit=54941 \
-attr uexp=0.17 \
-attr vmax=100000 \
-attr neff=0.01001 \
-attr delta=1.129 \
-attr "@nlv=W=\$w\nL=\$l" \
-spos $sfile 421 828
$db load port d inout
$db load port g input
$db load port s inout
$db load port b input
$db load primitive _CAP_ CAP \
-attr {@nlv=$C}
$db load port + inout
$db load port - inout
$db load module buf1 \
-spos $sfile 829 1290
$db load port O1 output \
-spos $sfile 842 844
$db load port I input \
-spos $sfile 845 846
$db load inst c0 _CAP_ \
-attr C=2.178e-17 \
-spos $sfile 847 867
$db load inst c2 _CAP_ \
-attr C=3.50895e-16 \
-spos $sfile 885 907
$db load inst c3 _CAP_ \
-attr C=1.7932e-16 \
-spos $sfile 907 928
$db load inst c4 _CAP_ \
-attr C=9.765e-17 \
-spos $sfile 928 947
$db load inst m5 cmosn \
-attr w=1.5e-06 \
-attr l=4e-07 \
-attr as=8.75e-13 \
-attr ad=1.65e-12 \
-attr ps=2.8e-06 \
-attr pd=5.2e-06 \
-spos $sfile 947 1035
$db load inst m6 cmosn \
-attr w=5e-07 \
-attr l=4e-07 \
-attr as=9.1e-13 \
-attr ad=8.75e-13 \
-attr ps=4e-06 \
-attr pd=2.8e-06 \
-spos $sfile 1035 1117
$db load inst m7 cmosp \
-attr w=2.7e-06 \
-attr l=4e-07 \
-attr as=1.575e-12 \
-attr ad=2.97e-12 \
-attr ps=4e-06 \
-attr pd=7.6e-06 \
-spos $sfile 1117 1204
$db load inst m8 cmosp \
-attr w=9e-07 \
-attr l=4e-07 \
-attr as=9.9e-13 \
-attr ad=1.575e-12 \
-attr ps=4e-06 \
-attr pd=4e-06 \
-spos $sfile 1204 1285
$db load net O1 -port O1 \
-pin c3 - \
-pin m5 d \
-pin m7 d \
-spos $sfile 1120 1122 \
-spos $sfile 950 952 \
-spos $sfile 914 916 \
-spos $sfile 842 844
$db load net I -port I \
-pin m8 g \
-pin c4 - \
-pin m6 g \
-spos $sfile 1211 1212 \
-spos $sfile 1042 1043 \
-spos $sfile 935 936 \
-spos $sfile 870 871 \
-spos $sfile 845 846
$db load net VDD \
-pin c0 + \
-pin m7 s \
-pin m7 b \
-pin m8 d \
-pin m8 b \
-spos $sfile 1216 1219 \
-spos $sfile 1207 1210 \
-spos $sfile 1130 1133 \
-spos $sfile 1126 1129 \
-spos $sfile 850 853 \
-flag power
$db load net n5 \
-pin c0 - \
-pin m8 s \
-pin c2 - \
-pin m5 g \
-pin m6 s \
-pin m7 g \
-spos $sfile 1213 1215 \
-spos $sfile 1123 1125 \
-spos $sfile 1044 1046 \
-spos $sfile 953 955 \
-spos $sfile 892 894 \
-spos $sfile 872 874 \
-spos $sfile 854 856
$db load net GND \
-pin c2 + \
-pin c3 + \
-pin c4 + \
-pin m5 s \
-pin m5 b \
-pin m6 d \
-pin m6 b \
-spos $sfile 1047 1050 \
-spos $sfile 1038 1041 \
-spos $sfile 960 963 \
-spos $sfile 956 959 \
-spos $sfile 931 934 \
-spos $sfile 910 913 \
-spos $sfile 888 891 \
-flag ground
# ======================
$db load module MUX4BIT
#
# created by verilog2tcl, version 2.9
# -outdir out2
# -view
#
$db load port Y0 output
$db load port Y1 output
$db load port Y2 output
$db load port Y3 output
$db load port A0 input
$db load port A1 input
$db load port A2 input
$db load port A3 input
$db load port B0 input
$db load port B1 input
$db load port B2 input
$db load port B3 input
$db load port SEL input
$db load inst U1 not1
$db load inst U2 not1
$db load inst U3 and2
$db load inst U4 and2
$db load inst U5 and2
$db load inst U6 and2
$db load inst U7 and2
$db load inst U8 and2
$db load inst U9 and2
$db load inst U10 and2
$db load inst U11 or2
$db load inst U12 or2
$db load inst U13 or2
$db load inst U14 or2
$db load net Y0 -port Y0 -pin U11 O
$db load net Y1 -port Y1 -pin U12 O
$db load net Y2 -port Y2 -pin U13 O
$db load net Y3 -port Y3 -pin U14 O
$db load net A0 -port A0 -pin U3 B
$db load net A1 -port A1 -pin U5 B
$db load net A2 -port A2 -pin U7 B
$db load net A3 -port A3 -pin U9 B
$db load net B0 -port B0 -pin U4 B
$db load net B1 -port B1 -pin U6 B
$db load net B2 -port B2 -pin U8 B
$db load net B3 -port B3 -pin U10 B
$db load net SEL -port SEL -pin U1 I
$db load net CHOOSE_BUF -pin U10 A \
-pin U8 A -pin U6 A -pin U4 A \
-pin U2 O1
$db load net CHOOSE_NOT -pin U9 A -pin U7 A \
-pin U5 A -pin U3 A -pin U2 I \
-pin U1 O1
$db load net PICK_A1 -pin U11 A -pin U3 O
$db load net PICK_B1 -pin U11 B -pin U4 O
$db load net A5 -pin U12 A -pin U5 O
$db load net A6 -pin U12 B -pin U6 O
$db load net A7 -pin U13 A -pin U7 O
$db load net A8 -pin U13 B -pin U8 O
$db load net A9 -pin U14 A -pin U9 O
$db load net A10 -pin U14 B -pin U10 O
# ======================
$db load module BUF8
#
# created by verilog2tcl, version 2.9
# -outdir out2
# -view
#
$db load portBus O output 8 {O[7]} {O[6]} {O[5]} {O[4]} {O[3]} \
{O[2]} {O[1]} {O[0]}
$db load portBus I input 8 {I[7]} {I[6]} {I[5]} {I[4]} {I[3]} \
{I[2]} {I[1]} {I[0]}
$db load inst BUF0 buf1
$db load inst BUF1 buf1
$db load inst BUF2 buf1
$db load inst BUF3 buf1
$db load inst BUF4 buf1
$db load inst BUF5 buf1
$db load inst BUF6 buf1
$db load inst BUF7 buf1
$db load net {O[0]} -port {O[0]} -pin BUF0 O1
$db load net {O[1]} -port {O[1]} -pin BUF1 O1
$db load net {O[2]} -port {O[2]} -pin BUF2 O1
$db load net {O[3]} -port {O[3]} -pin BUF3 O1
$db load net {O[4]} -port {O[4]} -pin BUF4 O1
$db load net {O[5]} -port {O[5]} -pin BUF5 O1
$db load net {O[6]} -port {O[6]} -pin BUF6 O1
$db load net {O[7]} -port {O[7]} -pin BUF7 O1
$db load netBus {O[7:0]} 8 {O[0]} {O[1]} {O[2]} {O[3]} \
{O[4]} {O[5]} {O[6]} {O[7]}
$db load net {I[0]} -port {I[0]} -pin BUF0 I
$db load net {I[1]} -port {I[1]} -pin BUF1 I
$db load net {I[2]} -port {I[2]} -pin BUF2 I
$db load net {I[3]} -port {I[3]} -pin BUF3 I
$db load net {I[4]} -port {I[4]} -pin BUF4 I
$db load net {I[5]} -port {I[5]} -pin BUF5 I
$db load net {I[6]} -port {I[6]} -pin BUF6 I
$db load net {I[7]} -port {I[7]} -pin BUF7 I
$db load netBus {I[7:0]} 8 {I[0]} {I[1]} {I[2]} {I[3]} \
{I[4]} {I[5]} {I[6]} {I[7]}
# ======================
$db load module SHFLOGIC
#
# created by verilog2tcl, version 2.9
# -outdir out2
# -view
#
$db load port CARRYOUT output
$db load portBus BO8 output 8 {BO8[7]} {BO8[6]} {BO8[5]} {BO8[4]} \
{BO8[3]} {BO8[2]} {BO8[1]} {BO8[0]}
$db load portBus ALU8 input 8 {ALU8[7]} {ALU8[6]} {ALU8[5]} \
{ALU8[4]} {ALU8[3]} {ALU8[2]} {ALU8[1]} {ALU8[0]}
$db load port CNPLUS4BAR input
$db load port I3 input
$db load port I4 input
$db load port I5 input
$db load port ID7 input
$db load port ID16 input
$db load port ID15 input
$db load port ALUOUTEN input
$db load port CARRYIN input
# ======================
$db load module FLAGUNIT
#
# created by verilog2tcl, version 2.9
# -outdir out2
# -view
#
$db load port BUSOUT0 output
$db load port BUSOUT4 output
$db load port BUSOUT6 output
$db load port BUSOUT2 output
$db load port BUSOUT7 output
$db load port MUXCC output
$db load port MUXCCBAR output
$db load port ALUCYOUT output
$db load port AC_SET output
$db load port M3 input
$db load port M2 input
$db load port M1 input
$db load port T4 input
$db load port T3 input
$db load port T2 input
$db load port IBUS0 input
$db load port IBUS2 input
$db load port IBUS4 input
$db load port IBUS6 input
$db load port IBUS7 input
$db load port ALUCRYIN input
$db load port ACFLAG input
$db load port ZFLAG input
$db load port PFLAG input
$db load port SFLAG input
$db load port I3 input
$db load port CLKBAR input
$db load port ID1 input
$db load port ID4 input
$db load port ID5 input
$db load port ID6 input
$db load port ID7 input
$db load port ID8 input
$db load port ID9 input
$db load port ID10 input
$db load port ID11 input
$db load port ID12 input
$db load port ID13 input
$db load port ID14 input
$db load port ID15 input
$db load port ID16 input
$db load port ID18 input
$db load port ID19 input
$db load inst U1 not1
$db load inst U2 nor3
$db load inst U3 and2
$db load inst U4 and2
$db load inst U5 or2
$db load inst U6 MUX4BIT
$db load inst U7 and2
$db load inst U8 and2
$db load inst U10 MUX4BIT
$db load inst U13 DFF
$db load inst U131 not1
$db load inst U132 or4
$db load inst U14 DFF
$db load inst U15 DFF
$db load inst U15A not1
$db load inst U16 DFF
$db load inst U16A not1
$db load inst U17 DFF
$db load inst U17A not1
$db load inst U18 nand2
$db load inst U19 nand2
$db load inst U20 nand2
$db load inst U21 nand2
$db load inst U22 nand2
$db load inst U24 nor2
$db load inst U27A buf1
$db load inst U28A buf1
$db load inst U47 and8
$db load inst U48 or2
$db load inst U49 or2
$db load inst U50 or2
$db load inst U51 or2
$db load inst U52 or2
$db load inst U53 or2
$db load inst U54 or2
$db load inst U55 or2
$db load inst U60 not1
$db load inst U61 buf1
$db load inst V2 not1
$db load inst V3 and2
$db load inst V4 nor2
$db load inst V5 and5
$db load inst V6 and2
$db load inst V10 nor2
$db load inst V11 nor3
$db load inst V12 nor3
$db load inst V13 nor3
$db load inst V14 nor3
$db load inst V15 nor3
$db load inst V16 nor2
$db load inst V18 and2
$db load inst V19 and2
$db load inst V20 and2
$db load inst V21 and2
$db load inst V22 and2
$db load inst V23 and2
$db load inst V24 or2
$db load inst V25 or3
$db load inst V26 or2
$db load inst V27 or2
$db load inst V28 or2
$db load inst V29 nor2
$db load inst V30 nor3
$db load inst V31 or2
$db load inst V32 and2
$db load inst V33 not1
$db load inst V40 nand2
$db load inst V41 or2
$db load net BUSOUT0 -port BUSOUT0 \
-pin U18 O
$db load net BUSOUT4 -port BUSOUT4 \
-pin U19 O
$db load net BUSOUT6 -port BUSOUT6 \
-pin U20 O
$db load net BUSOUT2 -port BUSOUT2 \
-pin U21 O
$db load net BUSOUT7 -port BUSOUT7 \
-pin U22 O
$db load net MUXCC -port MUXCC -pin U61 O1
$db load net MUXCCBAR -port MUXCCBAR \
-pin U60 O1
$db load net ALUCYOUT -port ALUCYOUT \
-pin U27A O1
$db load net AC_SET -port AC_SET -pin U28A O1
$db load net M3 -port M3 -pin V6 B
$db load net M2 -port M2 -pin V10 A \
-pin V6 A -pin U24 A
$db load net M1 -port M1 -pin V29 A \
-pin V4 A
$db load net T4 -port T4 -pin V29 B
$db load net T3 -port T3 -pin V16 A \
-pin V10 B
$db load net T2 -port T2 -pin V4 B \
-pin U24 B -pin U132 D
$db load net IBUS0 -port IBUS0 -pin U3 A
$db load net IBUS2 -port IBUS2 -pin U6 B2
$db load net IBUS4 -port IBUS4 -pin U6 B0
$db load net IBUS6 -port IBUS6 -pin U6 B1
$db load net IBUS7 -port IBUS7 -pin U6 B3
$db load net ALUCRYIN -port ALUCRYIN \
-pin U4 B
$db load net ACFLAG -port ACFLAG -pin U6 A0
$db load net ZFLAG -port ZFLAG -pin U6 A1
$db load net PFLAG -port PFLAG -pin U6 A2
$db load net SFLAG -port SFLAG -pin U6 A3
$db load net I3 -port I3 -pin V33 I
$db load net CLKBAR -port CLKBAR -pin U17 CK \
-pin U16 CK -pin U15 CK \
-pin U14 CK -pin U8 B
$db load net ID1 -port ID1 -pin V15 B \
-pin V11 B
$db load net VCC -flag power -pin U17 CLR -pin U17 SET \
-pin U16 CLR -pin U16 SET \
-pin U15 CLR -pin U15 SET \
-pin U14 CLR -pin U14 SET \
-pin U13 CLR
$db load net ID4 -port ID4 -pin V3 A
$db load net ID5 -port ID5 -pin V3 B \
-pin U2 C
$db load net ID6 -port ID6 -pin V41 B
$db load net ID7 -port ID7 -pin V30 A \
-pin V14 B -pin U132 A
$db load net ID8 -port ID8 -pin V5 A \
-pin U51 B
$db load net ID9 -port ID9 -pin V5 B \
-pin U50 B
$db load net ID10 -port ID10 -pin V5 C \
-pin U49 B
$db load net ID11 -port ID11 -pin V5 D \
-pin U48 B
$db load net ID12 -port ID12 -pin V30 B \
-pin U53 B
$db load net ID13 -port ID13 -pin U52 B
$db load net ID14 -port ID14 -pin V13 C \
-pin V11 C -pin V2 I -pin U55 B \
-pin U132 B -pin U2 B
$db load net ID15 -port ID15 -pin V5 E \
-pin U54 B
$db load net ID16 -port ID16 -pin V30 C \
-pin V15 A -pin V14 A -pin V13 A \
-pin V12 A -pin U132 C
$db load net ID18 -port ID18 -pin V40 A
$db load net ID19 -port ID19 -pin V41 A \
-pin V11 A -pin U2 A
$db load net E0 -pin V27 O -pin U10 SEL
$db load net E1 -pin V28 O -pin U8 A
$db load net F4 -pin V25 B -pin V18 O \
-pin U6 SEL -pin U3 B -pin U1 I
$db load net N1 -pin U4 A -pin U1 O1
$db load net PUSH_PSW -pin U7 B -pin U2 O
$db load net N3 -pin U5 A -pin U3 O
$db load net N4 -pin U5 B -pin U4 O
$db load net N5 -pin U13 D -pin U5 O
$db load net N7 -pin U22 B -pin U21 B \
-pin U20 B -pin U19 B -pin U18 B \
-pin U7 O
$db load net N8 -pin U13 CK -pin U8 O
$db load net M2T2 -pin U24 O -pin U7 A
$db load net N132 -pin U132 O -pin U13 SET
$db load net QMUX0 -pin U10 B0 -pin U6 Y0
$db load net QMUX1 -pin U10 B1 -pin U6 Y1
$db load net QMUX2 -pin U10 B2 -pin U6 Y2
$db load net QMUX3 -pin U10 B3 -pin U6 Y3
$db load net FLAG_BUS0 -pin U14 D -pin U10 Y0
$db load net FLAG_BUS1 -pin U15 D -pin U10 Y1
$db load net FLAG_BUS2 -pin U16 D -pin U10 Y2
$db load net FLAG_BUS3 -pin U17 D -pin U10 Y3
$db load net CARRY -pin U48 A -pin U27A I \
-pin U18 A -pin U131 I \
-pin U13 Q
$db load net AUX_CARRY -pin U28A I \
-pin U19 A -pin U14 Q -pin U10 A0
$db load net ZERO_DETECT -pin U50 A \
-pin U20 A -pin U15A I \
-pin U15 Q -pin U10 A1
$db load net PARITY -pin U52 A -pin U21 A \
-pin U16A I -pin U16 Q \
-pin U10 A2
$db load net SIGN -pin U54 A -pin U22 A \
-pin U17A I -pin U17 Q \
-pin U10 A3
$db load net G1 -pin U49 A -pin U131 O1
$db load net G3 -pin U51 A -pin U15A O1
$db load net G4 -pin U53 A -pin U16A O1
$db load net G5 -pin U55 A -pin U17A O1
$db load net MUXCC_BUF -pin U61 I -pin U60 I \
-pin U47 O
$db load net P2 -pin V12 C -pin V2 O1
$db load net P3 -pin V13 B -pin V12 B \
-pin V3 O
$db load net P5 -pin V14 C -pin V5 O
$db load net P6 -pin V16 B -pin V6 O
$db load net P10 -pin V20 A -pin V18 A \
-pin V10 O
$db load net POP_PSW -pin V18 B -pin V11 O
$db load net P12 -pin V19 B -pin V12 O
$db load net P13 -pin V20 B -pin V13 O
$db load net P14 -pin V21 A -pin V14 O
$db load net DAD -pin V22 A -pin V15 O
$db load net P16 -pin V22 B -pin V16 O
$db load net P19 -pin V24 A -pin V19 O
$db load net P20 -pin V24 B -pin V20 O
$db load net P21 -pin V26 A -pin V21 O
$db load net P22 -pin V26 B -pin V22 O
$db load net P23 -pin V25 A -pin V23 O
$db load net P24 -pin V27 A -pin V24 O
$db load net P25 -pin V28 A -pin V27 B \
-pin V25 O
$db load net P26 -pin V28 B -pin V26 O
$db load net P29 -pin V31 A -pin V29 O
$db load net DAA -pin V32 B -pin V30 O
$db load net P31 -pin V32 A -pin V31 O
$db load net P32 -pin V32 O -pin V25 C
$db load net P33 -pin V33 O1 -pin V15 C
$db load net P41 -pin V41 O -pin V40 B
$db load net F3 -pin V31 B -pin V23 B \
-pin V21 B -pin V19 A -pin V4 O
$db load net ALU_OPS_ -pin V40 O -pin V23 A
$db load net N48 -pin U48 O -pin U47 A
$db load net N49 -pin U49 O -pin U47 B
$db load net N50 -pin U50 O -pin U47 C
$db load net N51 -pin U51 O -pin U47 D
$db load net N52 -pin U52 O -pin U47 E
$db load net N53 -pin U53 O -pin U47 F
$db load net N54 -pin U54 O -pin U47 G
$db load net N55 -pin U55 O -pin U47 H
# ======================
$db load module ALU_CTRL
#
# created by verilog2tcl, version 2.9
# -outdir out2
# -view
#
$db load port M output
$db load port S0 output
$db load port S1 output
$db load port S2 output
$db load port S3 output
$db load port ENABLEDCY output
$db load port ID1 input
$db load port ID4 input
$db load port ID6 input
$db load port ID7 input
$db load port ID8 input
$db load port ID9 input
$db load port ID10 input
$db load port ID11 input
$db load port ID12 input
$db load port ID13 input
$db load port ID14 input
$db load port ID15 input
$db load port ID16 input
$db load port ID18 input
$db load port ID19 input
$db load port I3 input
$db load port M3 input
$db load port CY input
$db load port ID5 input
# ======================
$db load module OPRLOGIC
#
# created by verilog2tcl, version 2.9
# -outdir out2
# -view
#
$db load portBus BO8 output 8 {BO8[7]} {BO8[6]} {BO8[5]} {BO8[4]} \
{BO8[3]} {BO8[2]} {BO8[1]} {BO8[0]}
$db load portBus ALUA8 output 8 {ALUA8[7]} {ALUA8[6]} {ALUA8[5]} \
{ALUA8[4]} {ALUA8[3]} {ALUA8[2]} {ALUA8[1]} \
{ALUA8[0]}
$db load portBus ALUB8 output 8 {ALUB8[7]} {ALUB8[6]} {ALUB8[5]} \
{ALUB8[4]} {ALUB8[3]} {ALUB8[2]} {ALUB8[1]} \
{ALUB8[0]}
$db load portBus BIN input 8 {BIN[7]} {BIN[6]} {BIN[5]} {BIN[4]} \
{BIN[3]} {BIN[2]} {BIN[1]} {BIN[0]}
$db load port WRACC input
$db load port ACCOUTEN input
$db load port WRAUXACC input
$db load port WR2TEMP input
$db load port TEMP_OUT input
$db load port CLK input
$db load port T4 input
$db load port T2 input
$db load port AC_BUF input
$db load port CY input
$db load port CLEAR input
$db load port ID4 input
$db load port ID7 input
$db load port ID12 input
$db load port ID16 input
$db load port ENBUSTOAUX input
# ======================
$db load module PARITY1
#
# created by verilog2tcl, version 2.9
# -outdir out2
# -view
#
$db load port A input
$db load port B input
$db load port C input
$db load port D input
$db load port E input
$db load port F input
$db load port G input
$db load port H input
$db load port EVEN output
$db load inst U1 xor2
$db load inst U2 xor2
$db load inst U3 xor2
$db load inst U4 xor2
$db load inst U5 xor2
$db load inst U6 xor2
$db load inst U7 xnor2
$db load net EVEN -port EVEN -pin U7 O
$db load net A -port A -pin U1 A
$db load net B -port B -pin U1 B
$db load net C -port C -pin U2 A
$db load net D -port D -pin U2 B
$db load net E -port E -pin U3 A
$db load net F -port F -pin U3 B
$db load net G -port G -pin U4 A
$db load net H -port H -pin U4 B
$db load net L1 -pin U5 A -pin U1 O
$db load net L2 -pin U5 B -pin U2 O
$db load net L3 -pin U6 A -pin U3 O
$db load net L4 -pin U6 B -pin U4 O
$db load net L5 -pin U7 A -pin U5 O
$db load net L6 -pin U7 B -pin U6 O
# ======================
$db load module SN54181
#
# created by verilog2tcl, version 2.9
# -outdir out2
# -view
#
$db load port F3 output
$db load port F2 output
$db load port F1 output
$db load port F0 output
$db load port A_EQ_B output
$db load port X output
$db load port CN4 output
$db load port Y output
$db load port S3 input
$db load port S2 input
$db load port S1 input
$db load port S0 input
$db load port A3 input
$db load port A2 input
$db load port A1 input
$db load port A0 input
$db load port B3 input
$db load port B2 input
$db load port B1 input
$db load port B0 input
$db load port M input
$db load port CN input
$db load inst U1 not1
$db load inst U2 not1
$db load inst U3 not1
$db load inst U4 not1
$db load inst U5 and3
$db load inst U6 and3
$db load inst U7 and2
$db load inst U8 and2
$db load inst U9 buf1
$db load inst U10 and3
$db load inst U11 and3
$db load inst U12 and2
$db load inst U13 and2
$db load inst U14 buf1
$db load inst U15 and3
$db load inst U16 and3
$db load inst U17 and2
$db load inst U18 and2
$db load inst U19 buf1
$db load inst U20 and3
$db load inst U21 and3
$db load inst U22 and2
$db load inst U23 and2
$db load inst U24 buf1
$db load inst U25 nor2
$db load inst U26 nor3
$db load inst U27 nor2
$db load inst U28 nor3
$db load inst U29 nor2
$db load inst U30 nor3
$db load inst U31 nor2
$db load inst U32 nor3
$db load inst U33 xor2
$db load inst U34 xor2
$db load inst U35 xor2
$db load inst U36 xor2
$db load inst U37 not1
$db load inst U38 buf1
$db load inst U39 and2
$db load inst U40 and3
$db load inst U41 and4
$db load inst U42 nand5
$db load inst U43 nand4
$db load inst U44 and5
$db load inst U45 and4
$db load inst U46 and3
$db load inst U47 and2
$db load inst U48 and4
$db load inst U49 and3
$db load inst U50 and2
$db load inst U51 and3
$db load inst U52 and2
$db load inst U53 nand2
$db load inst U54 nor4
$db load inst U55 nor4
$db load inst U56 nor3
$db load inst U57 nor2
$db load inst U58 nand2
$db load inst U59 xor2
$db load inst U60 xor2
$db load inst U61 xor2
$db load inst U62 xor2
$db load inst U63 and4
$db load inst U54A buf1
$db load inst U59A buf1
$db load inst U60A buf1
$db load inst U61A buf1
$db load inst U62A buf1
$db load net F3 -port F3 -pin U59A O1
$db load net F2 -port F2 -pin U60A O1
$db load net F1 -port F1 -pin U61A O1
$db load net F0 -port F0 -pin U62A O1
$db load net A_EQ_B -port A_EQ_B -pin U63 O
$db load net X -port X -pin U43 O
$db load net CN4 -port CN4 -pin U58 O
$db load net Y -port Y -pin U54A O1
$db load net S3 -port S3 -pin U20 A \
-pin U15 B -pin U10 B -pin U5 B
$db load net S2 -port S2 -pin U21 B \
-pin U16 B -pin U11 B -pin U6 B
$db load net S1 -port S1 -pin U22 B \
-pin U17 B -pin U12 B -pin U7 B
$db load net S0 -port S0 -pin U23 A \
-pin U18 A -pin U13 A -pin U8 A
$db load net A3 -port A3 -pin U9 I \
-pin U6 A -pin U5 C
$db load net A2 -port A2 -pin U14 I \
-pin U11 A -pin U10 C
$db load net A1 -port A1 -pin U19 I \
-pin U16 A -pin U15 C
$db load net A0 -port A0 -pin U24 I \
-pin U21 A -pin U20 C
$db load net B3 -port B3 -pin U8 B \
-pin U5 A -pin U1 I
$db load net B2 -port B2 -pin U13 B \
-pin U10 A -pin U2 I
$db load net B1 -port B1 -pin U18 B \
-pin U15 A -pin U3 I
$db load net B0 -port B0 -pin U23 B \
-pin U20 B -pin U4 I
$db load net M -port M -pin U37 I
$db load net CN -port CN -pin U53 A \
-pin U51 A -pin U48 A -pin U44 D \
-pin U42 E
$db load net Z1 -pin U7 A -pin U6 C \
-pin U1 O1
$db load net Z2 -pin U12 A -pin U11 C \
-pin U2 O1
$db load net Z3 -pin U17 A -pin U16 C \
-pin U3 O1
$db load net Z4 -pin U22 A -pin U21 C \
-pin U4 O1
$db load net Z5 -pin U25 A -pin U5 O
$db load net Z6 -pin U25 B -pin U6 O
$db load net Z7 -pin U26 A -pin U7 O
$db load net Z8 -pin U26 B -pin U8 O
$db load net Z9 -pin U26 C -pin U9 O1
$db load net Z10 -pin U27 A -pin U10 O
$db load net Z11 -pin U27 B -pin U11 O
$db load net Z12 -pin U28 A -pin U12 O
$db load net Z13 -pin U28 B -pin U13 O
$db load net Z14 -pin U28 C -pin U14 O1
$db load net Z15 -pin U29 A -pin U15 O
$db load net Z16 -pin U29 B -pin U16 O
$db load net Z17 -pin U30 A -pin U17 O
$db load net Z18 -pin U30 B -pin U18 O
$db load net Z19 -pin U30 C -pin U19 O1
$db load net Z20 -pin U31 A -pin U20 O
$db load net Z21 -pin U31 B -pin U21 O
$db load net Z22 -pin U32 A -pin U22 O
$db load net Z23 -pin U32 B -pin U23 O
$db load net Z24 -pin U32 C -pin U24 O1
$db load net Z25 -pin U43 A -pin U42 A \
-pin U41 A -pin U40 A -pin U39 A \
-pin U33 A -pin U25 O
$db load net Z26 -pin U38 I -pin U33 B \
-pin U26 O
$db load net Z27 -pin U46 A -pin U45 A \
-pin U44 A -pin U43 B -pin U42 B \
-pin U41 B -pin U40 B -pin U34 A \
-pin U27 O
$db load net Z28 -pin U47 A -pin U39 B \
-pin U34 B -pin U28 O
$db load net Z29 -pin U49 A -pin U48 B \
-pin U45 B -pin U44 B -pin U43 C \
-pin U42 C -pin U41 C -pin U35 A \
-pin U29 O
$db load net Z30 -pin U50 A -pin U46 B \
-pin U40 C -pin U35 B -pin U30 O
$db load net Z31 -pin U51 B -pin U48 C \
-pin U44 C -pin U43 D -pin U42 D \
-pin U36 A -pin U31 O
$db load net Z32 -pin U52 A -pin U49 B \
-pin U45 C -pin U41 D -pin U36 B \
-pin U32 O
$db load net Z33 -pin U59 A -pin U33 O
$db load net Z34 -pin U60 A -pin U34 O
$db load net Z35 -pin U61 A -pin U35 O
$db load net Z36 -pin U62 A -pin U36 O
$db load net Z37 -pin U53 B -pin U52 B \
-pin U51 C -pin U50 B -pin U49 C \
-pin U48 D -pin U47 B -pin U46 C \
-pin U45 D -pin U44 E -pin U37 O1
$db load net Z38 -pin U54 A -pin U38 O1
$db load net Z39 -pin U54 B -pin U39 O
$db load net Z40 -pin U54 C -pin U40 O
$db load net Z41 -pin U54 D -pin U41 O
$db load net Z42 -pin U58 B -pin U42 O
$db load net Z44 -pin U55 A -pin U44 O
$db load net Z45 -pin U55 B -pin U45 O
$db load net Z46 -pin U55 C -pin U46 O
$db load net Z47 -pin U55 D -pin U47 O
$db load net Z48 -pin U56 A -pin U48 O
$db load net Z49 -pin U56 B -pin U49 O
$db load net Z50 -pin U56 C -pin U50 O
$db load net Z51 -pin U57 A -pin U51 O
$db load net Z52 -pin U57 B -pin U52 O
$db load net Z53 -pin U62 B -pin U53 O
$db load net Z55 -pin U59 B -pin U55 O
$db load net Z56 -pin U60 B -pin U56 O
$db load net Z57 -pin U61 B -pin U57 O
$db load net F3B -pin U59A I -pin U63 D \
-pin U59 O
$db load net F2B -pin U60A I -pin U63 C \
-pin U60 O
$db load net F1B -pin U61A I -pin U63 B \
-pin U61 O
$db load net F0B -pin U62A I -pin U63 A \
-pin U62 O
$db load net YB -pin U54A I -pin U58 A \
-pin U54 O
# ======================
$db load module ALU8BIT
#
# created by verilog2tcl, version 2.9
# -outdir out2
# -view
#
$db load portBus F8 output 8 {F8[7]} {F8[6]} {F8[5]} {F8[4]} \
{F8[3]} {F8[2]} {F8[1]} {F8[0]}
$db load port bad1 output
$db load port bad2 output
$db load port A_EQ_B output
$db load port X output
$db load port Y output
$db load port Z output
$db load port AC output
$db load port P output
$db load port CY output
$db load port S3 input
$db load port S2 input
$db load port S1 input
$db load port S0 input
$db load portBus A8 input 8 {A8[7]} {A8[6]} {A8[5]} {A8[4]} \
{A8[3]} {A8[2]} {A8[1]} {A8[0]}
$db load portBus B8 input 8 {B8[7]} {B8[6]} {B8[5]} {B8[4]} \
{B8[3]} {B8[2]} {B8[1]} {B8[0]}
$db load port CN input
$db load port M input
$db load inst U0 not1
$db load inst U1 not1
$db load inst U2 and2
$db load inst U3 and2
$db load inst U4 nor2
$db load inst U5 SN54181
$db load inst U6 SN54181
$db load inst U7 BUF8
$db load inst ZEROCK nor8
$db load inst PARITYCK PARITY1
$db load net A_EQ_B -port A_EQ_B -pin U6 A_EQ_B
$db load net X -port X -pin U6 X
$db load net Y -port Y -pin U6 Y
$db load net Z -port Z -pin ZEROCK O
$db load net AC -port AC -pin U0 O1
$db load net P -port P -pin PARITYCK EVEN
$db load net CY -port CY -pin U6 CN4
$db load net S3 -port S3 -pin U6 S3 \
-pin U5 S3
$db load net S2 -port S2 -pin U6 S2 \
-pin U5 S2
$db load net S1 -port S1 -pin U6 S1 \
-pin U5 S1
$db load net S0 -port S0 -pin U6 S0 \
-pin U5 S0
$db load net CN -port CN -pin U5 CN \
-pin U1 I
$db load net M -port M -pin U6 M -pin U5 M
$db load net NET1 -pin U2 A -pin U1 O1
$db load net NET2 -pin U4 A -pin U2 O
$db load net NET3 -pin U4 B -pin U3 O
$db load net NET4 -pin U5 X -pin U3 A
$db load net NET5 -pin U5 Y -pin U3 B \
-pin U2 B
$db load net NET6 -pin U6 CN -pin U4 O \
-pin U0 I
$db load net {F8[0]} -port {F8[0]} -pin U7 {O[0]}
$db load net {F8[1]} -port {F8[1]} -pin U7 {O[1]}
$db load net {F8[2]} -port {F8[2]} -pin U7 {O[2]}
$db load net {F8[3]} -port {F8[3]} -pin U7 {O[3]}
$db load net {F8[4]} -port {F8[4]} -pin U7 {O[4]}
$db load net {F8[5]} -port {F8[5]} -pin U7 {O[5]}
$db load net {F8[6]} -port {F8[6]} -pin U7 {O[6]}
$db load net {F8[7]} -port {F8[7]} -pin U7 {O[7]}
$db load netBus {F8[7:0]} 8 {F8[0]} {F8[1]} {F8[2]} \
{F8[3]} {F8[4]} {F8[5]} {F8[6]} {F8[7]}
$db load net {A8[3]} -port {A8[3]} -pin U5 A3
$db load net {A8[2]} -port {A8[2]} -pin U5 A2
$db load net {A8[1]} -port {A8[1]} -pin U5 A1
$db load net {A8[0]} -port {A8[0]} -pin U5 A0
$db load net {A8[7]} -port {A8[7]} -pin U6 A3
$db load net {A8[6]} -port {A8[6]} -pin U6 A2
$db load net {A8[5]} -port {A8[5]} -pin U6 A1
$db load net {A8[4]} -port {A8[4]} -pin U6 A0
$db load netBus {A8[7:0]} 8 {A8[3]} {A8[2]} {A8[1]} \
{A8[0]} {A8[7]} {A8[6]} {A8[5]} {A8[4]}
$db load net {B8[3]} -port {B8[3]} -pin U5 B3
$db load net {B8[2]} -port {B8[2]} -pin U5 B2
$db load net {B8[1]} -port {B8[1]} -pin U5 B1
$db load net {B8[0]} -port {B8[0]} -pin U5 B0
$db load net {B8[7]} -port {B8[7]} -pin U6 B3
$db load net {B8[6]} -port {B8[6]} -pin U6 B2
$db load net {B8[5]} -port {B8[5]} -pin U6 B1
$db load net {B8[4]} -port {B8[4]} -pin U6 B0
$db load netBus {B8[7:0]} 8 {B8[3]} {B8[2]} {B8[1]} \
{B8[0]} {B8[7]} {B8[6]} {B8[5]} {B8[4]}
$db load net {F_BUF8[3]} -pin PARITYCK E -pin ZEROCK E \
-pin U7 {I[3]} -pin U5 F3
$db load net {F_BUF8[2]} -pin PARITYCK F -pin ZEROCK F \
-pin U7 {I[2]} -pin U5 F2
$db load net {F_BUF8[1]} -pin PARITYCK G -pin ZEROCK G \
-pin U7 {I[1]} -pin U5 F1
$db load net {F_BUF8[0]} -pin PARITYCK H -pin ZEROCK H \
-pin U7 {I[0]} -pin U5 F0
$db load net {F_BUF8[7]} -pin PARITYCK A -pin ZEROCK A \
-pin U7 {I[7]} -pin U6 F3
$db load net {F_BUF8[6]} -pin PARITYCK B -pin ZEROCK B \
-pin U7 {I[6]} -pin U6 F2
$db load net {F_BUF8[5]} -pin PARITYCK C -pin ZEROCK C \
-pin U7 {I[5]} -pin U6 F1
$db load net {F_BUF8[4]} -pin PARITYCK D -pin ZEROCK D \
-pin U7 {I[4]} -pin U6 F0
$db load netBus {F_BUF8[7:0]} 8 {F_BUF8[3]} {F_BUF8[2]} \
{F_BUF8[1]} {F_BUF8[0]} {F_BUF8[7]} {F_BUF8[6]} \
{F_BUF8[5]} {F_BUF8[4]}
$db load net bad -port bad1 -port bad2 -pin U5 CN4 -pin U5 A_EQ_B
# ======================
$db load module ALULOGIC -top
#
# created by verilog2tcl, version 2.9
# -outdir out2
# -view
#
$db load portBus BO8 output 8 {BO8[7]} {BO8[6]} {BO8[5]} {BO8[4]} \
{BO8[3]} {BO8[2]} {BO8[1]} {BO8[0]}
$db load portBus BIN input 8 {BIN[7]} {BIN[6]} {BIN[5]} {BIN[4]} \
{BIN[3]} {BIN[2]} {BIN[1]} {BIN[0]}
$db load port WRACC input
$db load port ACCOUTEN input
$db load port WRAUXACC input
$db load port WR2TEMP input
$db load port TEMP_OUT input
$db load port MUXCC output
$db load port MUXCCBAR output
$db load port ID19 input
$db load port ID18 input
$db load port ID16 input
$db load portBus ID8_B input 8 {ID8_B[7]} {ID8_B[6]} {ID8_B[5]} \
{ID8_B[4]} {ID8_B[3]} {ID8_B[2]} {ID8_B[1]} \
{ID8_B[0]}
$db load port ID7 input
$db load port ID6 input
$db load port ID5 input
$db load port ID4 input
$db load port ID1 input
$db load port I5 input
$db load port I4 input
$db load port I3 input
$db load port M3 input
$db load port M2 input
$db load port M1 input
$db load port T4 input
$db load port T3 input
$db load port T2 input
$db load port CLKBAR input
$db load port ALUOUTEN input
$db load port REGRESET input
$db load port ENBUSTOAUX input
$db load inst A8B ALU8BIT
$db load inst OP_L OPRLOGIC
$db load inst AL_C ALU_CTRL
$db load inst FG_U FLAGUNIT
$db load inst SH_L SHFLOGIC
$db load net MUXCC -port MUXCC -pin FG_U MUXCC
$db load net MUXCCBAR -port MUXCCBAR \
-pin FG_U MUXCCBAR
$db load net WRACC -port WRACC -pin OP_L WRACC
$db load net ACCOUTEN -port ACCOUTEN \
-pin OP_L ACCOUTEN
$db load net WRAUXACC -port WRAUXACC \
-pin OP_L WRAUXACC
$db load net WR2TEMP -port WR2TEMP \
-pin OP_L WR2TEMP
$db load net TEMP_OUT -port TEMP_OUT \
-pin OP_L TEMP_OUT
$db load net ID19 -port ID19 -pin FG_U ID19 \
-pin AL_C ID19
$db load net ID18 -port ID18 -pin FG_U ID18 \
-pin AL_C ID18
$db load net ID16 -port ID16 -pin SH_L ID16 \
-pin FG_U ID16 -pin AL_C ID16 \
-pin OP_L ID16
$db load net ID7 -port ID7 -pin SH_L ID7 \
-pin FG_U ID7 -pin AL_C ID7 \
-pin OP_L ID7
$db load net ID6 -port ID6 -pin FG_U ID6 \
-pin AL_C ID6
$db load net ID5 -port ID5 -pin FG_U ID5 \
-pin AL_C ID5
$db load net ID4 -port ID4 -pin FG_U ID4 \
-pin AL_C ID4 -pin OP_L ID4
$db load net ID1 -port ID1 -pin FG_U ID1 \
-pin AL_C ID1
$db load net I5 -port I5 -pin SH_L I5
$db load net I4 -port I4 -pin SH_L I4
$db load net I3 -port I3 -pin SH_L I3 \
-pin FG_U I3 -pin AL_C I3
$db load net M3 -port M3 -pin FG_U M3 \
-pin AL_C M3
$db load net M2 -port M2 -pin FG_U M2
$db load net M1 -port M1 -pin FG_U M1
$db load net T4 -port T4 -pin FG_U T4 \
-pin OP_L T4
$db load net T3 -port T3 -pin FG_U T3
$db load net T2 -port T2 -pin FG_U T2 \
-pin OP_L T2
$db load net CLKBAR -port CLKBAR -pin FG_U CLKBAR \
-pin OP_L CLK
$db load net ALUOUTEN -port ALUOUTEN \
-pin SH_L ALUOUTEN
$db load net REGRESET -port REGRESET \
-pin OP_L CLEAR
$db load net ENBUSTOAUX -port ENBUSTOAUX \
-pin OP_L ENBUSTOAUX
$db load net S3 -pin AL_C S3 -pin A8B S3
$db load net S2 -pin AL_C S2 -pin A8B S2
$db load net S1 -pin AL_C S1 -pin A8B S1
$db load net S0 -pin AL_C S0 -pin A8B S0
$db load net M -pin AL_C M -pin A8B M
$db load net CN -pin AL_C ENABLEDCY \
-pin A8B CN
$db load net CY -pin SH_L CARRYIN -pin FG_U ALUCYOUT \
-pin AL_C CY -pin OP_L CY
$db load net CNPLUS4BAR -pin SH_L CNPLUS4BAR \
-pin A8B CY
$db load net ACSET -pin FG_U AC_SET \
-pin OP_L AC_BUF
$db load net AC_BUF -pin FG_U ACFLAG \
-pin A8B AC
$db load net P -pin FG_U PFLAG -pin A8B P
$db load net Z -pin FG_U ZFLAG -pin A8B Z
$db load net CARRYOUT -pin SH_L CARRYOUT \
-pin FG_U ALUCRYIN
$db load net {BO8[0]} -port {BO8[0]} -pin SH_L {BO8[0]} \
-pin FG_U BUSOUT0 -pin OP_L {BO8[0]}
$db load net {BO8[1]} -port {BO8[1]} -pin SH_L {BO8[1]} \
-pin OP_L {BO8[1]}
$db load net {BO8[2]} -port {BO8[2]} -pin SH_L {BO8[2]} \
-pin FG_U BUSOUT2 -pin OP_L {BO8[2]}
$db load net {BO8[3]} -port {BO8[3]} -pin SH_L {BO8[3]} \
-pin OP_L {BO8[3]}
$db load net {BO8[4]} -port {BO8[4]} -pin SH_L {BO8[4]} \
-pin FG_U BUSOUT4 -pin OP_L {BO8[4]}
$db load net {BO8[5]} -port {BO8[5]} -pin SH_L {BO8[5]} \
-pin OP_L {BO8[5]}
$db load net {BO8[6]} -port {BO8[6]} -pin SH_L {BO8[6]} \
-pin FG_U BUSOUT6 -pin OP_L {BO8[6]}
$db load net {BO8[7]} -port {BO8[7]} -pin SH_L {BO8[7]} \
-pin FG_U BUSOUT7 -pin OP_L {BO8[7]}
$db load netBus {BO8[7:0]} 8 {BO8[0]} {BO8[1]} {BO8[2]} \
{BO8[3]} {BO8[4]} {BO8[5]} {BO8[6]} {BO8[7]}
$db load net {BIN[0]} -port {BIN[0]} -pin FG_U IBUS0 -pin \
OP_L {BIN[0]}
$db load net {BIN[1]} -port {BIN[1]} -pin OP_L {BIN[1]}
$db load net {BIN[2]} -port {BIN[2]} -pin FG_U IBUS2 -pin \
OP_L {BIN[2]}
$db load net {BIN[3]} -port {BIN[3]} -pin OP_L {BIN[3]}
$db load net {BIN[4]} -port {BIN[4]} -pin FG_U IBUS4 -pin \
OP_L {BIN[4]}
$db load net {BIN[5]} -port {BIN[5]} -pin OP_L {BIN[5]}
$db load net {BIN[6]} -port {BIN[6]} -pin FG_U IBUS6 -pin \
OP_L {BIN[6]}
$db load net {BIN[7]} -port {BIN[7]} -pin FG_U IBUS7 -pin \
OP_L {BIN[7]}
$db load netBus {BIN[7:0]} 8 {BIN[0]} {BIN[1]} {BIN[2]} \
{BIN[3]} {BIN[4]} {BIN[5]} {BIN[6]} {BIN[7]}
$db load net {ID8_B[4]} -port {ID8_B[4]} -pin FG_U ID12 \
-pin AL_C ID12 -pin OP_L ID12
$db load net {ID8_B[0]} -port {ID8_B[0]} -pin FG_U ID8 \
-pin AL_C ID8
$db load net {ID8_B[1]} -port {ID8_B[1]} -pin FG_U ID9 \
-pin AL_C ID9
$db load net {ID8_B[2]} -port {ID8_B[2]} -pin FG_U ID10 \
-pin AL_C ID10
$db load net {ID8_B[3]} -port {ID8_B[3]} -pin FG_U ID11 \
-pin AL_C ID11
$db load net {ID8_B[5]} -port {ID8_B[5]} -pin FG_U ID13 \
-pin AL_C ID13
$db load net {ID8_B[6]} -port {ID8_B[6]} -pin FG_U ID14 \
-pin AL_C ID14
$db load net {ID8_B[7]} -port {ID8_B[7]} -pin SH_L ID15 \
-pin FG_U ID15 -pin AL_C ID15
$db load netBus {ID8_B[7:0]} 8 {ID8_B[4]} {ID8_B[0]} \
{ID8_B[1]} {ID8_B[2]} {ID8_B[3]} {ID8_B[5]} \
{ID8_B[6]} {ID8_B[7]}
$db load net {F8[0]} -pin SH_L {ALU8[0]} -pin A8B {F8[0]}
$db load net {F8[1]} -pin SH_L {ALU8[1]} -pin A8B {F8[1]}
$db load net {F8[2]} -pin SH_L {ALU8[2]} -pin A8B {F8[2]}
$db load net {F8[3]} -pin SH_L {ALU8[3]} -pin A8B {F8[3]}
$db load net {F8[4]} -pin SH_L {ALU8[4]} -pin A8B {F8[4]}
$db load net {F8[5]} -pin SH_L {ALU8[5]} -pin A8B {F8[5]}
$db load net {F8[6]} -pin SH_L {ALU8[6]} -pin A8B {F8[6]}
$db load net {F8[7]} -pin SH_L {ALU8[7]} -pin FG_U SFLAG \
-pin A8B {F8[7]}
$db load netBus {F8[7:0]} 8 {F8[0]} {F8[1]} {F8[2]} \
{F8[3]} {F8[4]} {F8[5]} {F8[6]} {F8[7]}
$db load net {A8[0]} -pin OP_L {ALUA8[0]} -pin A8B {A8[0]}
$db load net {A8[1]} -pin OP_L {ALUA8[1]} -pin A8B {A8[1]}
$db load net {A8[2]} -pin OP_L {ALUA8[2]} -pin A8B {A8[2]}
$db load net {A8[3]} -pin OP_L {ALUA8[3]} -pin A8B {A8[3]}
$db load net {A8[4]} -pin OP_L {ALUA8[4]} -pin A8B {A8[4]}
$db load net {A8[5]} -pin OP_L {ALUA8[5]} -pin A8B {A8[5]}
$db load net {A8[6]} -pin OP_L {ALUA8[6]} -pin A8B {A8[6]}
$db load net {A8[7]} -pin OP_L {ALUA8[7]} -pin A8B {A8[7]}
$db load netBus {A8[7:0]} 8 {A8[0]} {A8[1]} {A8[2]} \
{A8[3]} {A8[4]} {A8[5]} {A8[6]} {A8[7]}
$db load net {B8[0]} -pin OP_L {ALUB8[0]} -pin A8B {B8[0]}
$db load net {B8[1]} -pin OP_L {ALUB8[1]} -pin A8B {B8[1]}
$db load net {B8[2]} -pin OP_L {ALUB8[2]} -pin A8B {B8[2]}
$db load net {B8[3]} -pin OP_L {ALUB8[3]} -pin A8B {B8[3]}
$db load net {B8[4]} -pin OP_L {ALUB8[4]} -pin A8B {B8[4]}
$db load net {B8[5]} -pin OP_L {ALUB8[5]} -pin A8B {B8[5]}
$db load net {B8[6]} -pin OP_L {ALUB8[6]} -pin A8B {B8[6]}
$db load net {B8[7]} -pin OP_L {ALUB8[7]} -pin A8B {B8[7]}
$db load netBus {B8[7:0]} 8 {B8[0]} {B8[1]} {B8[2]} \
{B8[3]} {B8[4]} {B8[5]} {B8[6]} {B8[7]}
# ==========
# Update GUI
#
gui database changed $db
|