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****************************************
Report : model_debug_paths
-path_type full_clock_expanded
-nets
-transition_time
-full_transition_time
-capacitance
-wire_delay
-show_path_index
-show_path_id
-crosstalk_delta
-rail_voltage
-final_voltage
-nosplit
Design : gl85
Version: hand made dummy data; for demo purposes only
Date : 2017-02-20 17:21:26
****************************************
Net Types (NT):
D - Data input
O - Data output
SZ - Data turnoff output
Z - Turnoff
E - Turnoff enable
C - Clock
CX - Clock with dynamic simulation
L - Latch
R - Register File Latch
A - Adjusted latch
RA - Adjusted Register File latch
G - Gated clock
T - Transparent gated clock
SC - Stopped clock
U - User defined constraint
DU - User defined data-to-data constraint
M - Timing model
LP - Latch to latch loop
PC - Precharge Clock
EC - Eval Clock
PP - Precharge PC and Predischarge EC
PN - Precharge EC and Predischarge PC
N1-8 - N-domino precharge node (see report_paths man page)
n1-8 - N-domino input (see report_paths man page)
P1-8 - P-domino precharge node (see report_paths man page)
p1-8 - P-domino input (see report_paths man page)
GC - Generated Clock
$ - Simultaneous switching inputs (see report_paths man page)
& - Net has backannotated parasitics
Item: 1
Path ID: 1
Startpoint: CLK (in port)
Endpoint: XIR/XB8/XU9/XBUF7/m8/g
Path Type: max_clock
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 0.000 0.140 0.175 0.022 C& r CLK (in) x
0.002 0.002 0.002 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.022 C& r XIR/XB8/XU8/m8/g (x) x
0.024 0.022 0.002 0.000 1.000 0.000 0.037 0.047 0.900 0.000 0.008 C& f XIR/XB8/XU8/m6/g (x) x
0.037 0.013 0.005 0.000 1.000 0.000 0.032 0.040 0.900 0.899 0.088 C& r XIR/XB8/XR0/m11/g (x) x
0.049 0.012 0.003 0.000 1.000 0.000 0.025 0.032 0.900 0.002 0.026 C& f XIR/XB8/XR0/m22/g (x) x
0.058 0.009 0.003 0.000 1.000 0.000 0.019 0.024 0.900 0.899 0.065 C& r XIR/XB8/XU9/XBUF7/m8/g (x) x
0.058 clock arrival time
0.058 0.000 0.000 Total
(Path is unconstrained)
Item: 2
Path ID: 2
Startpoint: CLK (in port)
Endpoint: CLKOUT (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 0.000 0.140 0.175 0.022 C& r CLK (in) x
0.002 0.002 0.002 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.022 C& r XT9/m2/g (x) x
0.024 0.022 0.002 0.000 1.000 0.000 0.037 0.047 0.900 0.000 0.008 DU& f XBUF5/m6/g (x) x
0.037 0.013 0.005 0.000 1.000 0.000 0.032 0.040 0.900 0.899 0.088 C& r XBUF5/m5/g (x) x
0.132 0.004 0.001 0.000 1.000 0.000 0.009 0.011 0.900 0.899 0.022 O& f CLKOUT (out) x
0.132 data arrival time
0.132 0.000 0.000 Total
0.360 0.360 clock rclk (rise)
0.360 0.000 output external delay
0.360 0.000 clock uncertainty
0.360 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0.360 data required time
-0.132 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0.228 slack (MET)
Item: 3
Path ID: 3
Startpoint: RESETINBAR (in port)
Endpoint: HLDA (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
1000.000 0.000 0.140 0.175 0.035 D& r RESETINBAR (in) x
1000.004 0.004 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r XC2/XHDL/XU2/m7/g (x) x
1000.028 0.024 0.004 0.000 1.000 0.000 0.046 0.057 0.900 0.000 0.010 & f XC2/XHDL/XU2/m19/g (x) x
1000.038 0.010 0.003 0.000 1.000 0.000 0.026 0.033 0.900 0.898 0.024 & r XC2/XHDL/XU3/m6/g (x) x
1000.050 0.012 0.003 0.000 1.000 0.000 0.024 0.029 0.900 0.001 0.033 & f XC2/XHDL/XU3/m5/g (x) x
1000.050 0.012 0.003 0.000 1.000 0.000 0.024 0.029 0.900 0.001 0.033 & r XC2/XBUF3/m6/g (x) x
1000.050 0.012 0.003 0.000 1.000 0.000 0.024 0.029 0.900 0.001 0.033 & f XC2/XBUF3/m5/g (x) x
1000.054 0.004 0.000 0.000 1.000 0.000 0.007 0.008 0.900 0.900 0.018 O& r HLDA (out) x
1000.054 data arrival time
0.054 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
0.000 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0.000 data required time
-1000.054 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-1000.054 slack (VIOLATED)
Item: 4
Path ID: 4
Startpoint: RESETINBAR (in port)
Endpoint: XC2/XU1/XU2/m10/g
Path Type: max
Constraint: en gated clock setup (cvm -> clkdrvc_ap_120f)
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
1000.000 0.000 0.140 0.175 0.007 D& r RESETINBAR (in) x
1000.001 0.001 0.001 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.007 & r XC2/XHDL/XU2/m7/g (somemodel) somenet
1.421 0.029 -998.610 0.001 0.000 1.000 -0.000 0.051 0.064 0.900 0.001 0.002 A& f XC2/XHDL/XU2/m19/g (somemodel) somenet
1.441 0.029 -998.610 0.001 0.000 1.000 -0.000 0.051 0.064 0.900 0.001 0.002 A& r XC2/XHDL/XU3/m6/g (somemodel) somenet
1.461 0.029 -998.610 0.001 0.000 1.000 -0.000 0.051 0.064 0.900 0.001 0.002 A& r XC2/XHDL/XU3/m5/g (somemodel) somenet
1.481 0.029 -998.610 0.001 0.000 1.000 -0.000 0.051 0.064 0.900 0.001 0.002 A& f XC2/XU1/XU2/m10/g (somemodel) somenet
1.503 data arrival time
0.113 -998.610 0.000 Total
0.360 0.360 0.140 0.175 0.022 C& r CLK (in) x
0.362 0.002 0.002 0.000 1.000 -0.000 0.140 0.175 0.900 0.900 0.022 C& r XIT/XF1/XU18/m8/g (somemodel) somenet
0.383 0.021 0.002 -0.001 0.946 0.000 0.037 0.047 0.900 0.000 0.008 C$& f XIT/XF1/XU18/m19/g (somemodel) somenet
0.397 0.014 0.007 -0.001 0.955 -0.000 0.026 0.032 0.900 0.899 0.088 C$& r XIT/XF1/XU36/m6/g (somemodel) somenet
0.407 0.014 0.007 -0.001 0.955 -0.000 0.026 0.032 0.900 0.899 0.088 C$& f XIT/XF1/XU36/m5/g (somemodel) somenet
0.417 0.014 0.007 -0.001 0.955 -0.000 0.026 0.032 0.900 0.899 0.088 C$& r XIT/XF3/m7/g (somemodel) somenet
0.427 0.014 0.007 -0.001 0.955 -0.000 0.026 0.032 0.900 0.899 0.088 C$& f XIT/XF3/m6/g (somemodel) somenet
0.437 0.014 0.007 -0.001 0.955 -0.000 0.026 0.032 0.900 0.899 0.088 C$& r XC2/XU1/XINV0/m2/g (somemodel) somenet
0.447 0.014 0.007 -0.001 0.955 -0.000 0.026 0.032 0.900 0.899 0.088 C$& f XC2/XU1/XU2/m11/g (somemodel) somenet
0.037 0.360 -0.000 Total
0.449 -0.008 setup time
0.449 0.000 clock uncertainty
0.449 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0.449 data required time
-1.503 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-1.114 slack (VIOLATED)
Item: 5
Path ID: 5
Startpoint: READY (in port)
Endpoint: XC2/XU1/XCOMP2/XU17/m6/g
Path Type: max
Constraint: en gated clock setup (cvm -> clkdrvc_ap_120f)
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
1000.000 0.000 0.140 0.175 0.007 D& r READY (in) x
1000.001 0.001 0.001 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.007 & r XC2/XU1/XINV4/m3/g (x) x
1.421 0.029 -998.610 0.001 0.000 1.000 -0.000 0.051 0.064 0.900 0.001 0.002 A& f XC2/XU1/XCOMP2/XU17/m6/g (x) x
1.503 data arrival time
0.113 -998.610 0.000 Total
0.360 0.360 0.140 0.175 0.022 C& r CLK (in) x
0.362 0.002 0.002 0.000 1.000 -0.000 0.140 0.175 0.900 0.900 0.022 C& r XC2/XU1/XDF1/m11/g (x) x
0.383 0.021 0.002 -0.001 0.946 0.000 0.037 0.047 0.900 0.000 0.008 C$& f XC2/XU1/XDF1/m22/g (x) x
0.397 0.014 0.007 -0.001 0.955 -0.000 0.026 0.032 0.900 0.899 0.088 C$& r XC2/XU1/XBUF3/m8/g (x) x
0.397 0.014 0.007 -0.001 0.955 -0.000 0.026 0.032 0.900 0.899 0.088 C$& f XC2/XU1/XBUF3/m7/g (x) x
0.397 0.014 0.007 -0.001 0.955 -0.000 0.026 0.032 0.900 0.899 0.088 C$& r XC2/XU1/XCOMP2/XU2/m2/g (x) x
0.037 0.360 -0.000 Total
0.389 -0.008 setup time
0.389 0.000 clock uncertainty
0.389 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0.389 data required time
-1.503 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-1.114 slack (VIOLATED)