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1050 | ****************************************
Report : model_debug_paths
-path_type full_clock_expanded
-nets
-transition_time
-full_transition_time
-capacitance
-wire_delay
-show_path_index
-show_path_id
-crosstalk_delta
-rail_voltage
-final_voltage
-nosplit
Design : mydesign
Version: hand made dummy data; for demo purposes only
Date : 2019-05-10 12:57:54
****************************************
Net Types (NT):
D - Data input
O - Data output
SZ - Data turnoff output
Z - Turnoff
E - Turnoff enable
C - Clock
CX - Clock with dynamic simulation
L - Latch
R - Register File Latch
A - Adjusted latch
RA - Adjusted Register File latch
G - Gated clock
T - Transparent gated clock
SC - Stopped clock
U - User defined constraint
DU - User defined data-to-data constraint
M - Timing model
LP - Latch to latch loop
PC - Precharge Clock
EC - Eval Clock
PP - Precharge PC and Predischarge EC
PN - Precharge EC and Predischarge PC
N1-8 - N-domino precharge node (see report_paths man page)
n1-8 - N-domino input (see report_paths man page)
P1-8 - P-domino precharge node (see report_paths man page)
p1-8 - P-domino input (see report_paths man page)
GC - Generated Clock
$ - Simultaneous switching inputs (see report_paths man page)
& - Net has backannotated parasitics
Item: 1
Path ID: 1
Startpoint: s13_err_i (in port)
Endpoint: eth_top/wishbone/tx_burst_cnt_38/d[0] (tx_burst_cnt_38) n1020
Path Type: max
Constraint: en gated clock setup
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& f s13_err_i (in) s13_err_i
0.736 0.736 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s13_err_i (wb_conmax_top) s13_err_i
0.783 0.047 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s13/wb_err_i (s13) s13_err_i
0.943 0.160 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s13/i69/a1 (i69) wb_err_i
1.043 0.100 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s13/i69/o (i69) m3_err_o
1.435 0.392 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s13/m3_err_o (s13) m3s13_err
1.868 0.433 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m3/s13_err_i (m3) m3s13_err
2.052 0.184 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m3/Mux_214/data[13] (Mux_214) s13_err_i
3.048 0.996 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m3/Mux_214/o (Mux_214) wb_err_o
3.130 0.082 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m3/wb_err_o (m3) m3_err_o
3.496 0.367 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m3_err_o (wb_conmax_top) m3_err_o
3.789 0.292 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r eth_top/m_wb_err_i (eth_top) m3_err_o
4.630 0.841 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f eth_top/wishbone/m_wb_err_i (wishbone) m_wb_err_i
5.239 0.609 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f eth_top/wishbone/i246/a1 (i246) m_wb_err_i
5.999 0.760 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r eth_top/wishbone/i246/o (i246) MasterAccessFinished
6.696 0.697 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f eth_top/wishbone/equal_267/a[3] (equal_267) MasterAccessFinished
7.512 0.816 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f eth_top/wishbone/equal_267/o (equal_267) n933
8.022 0.510 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r eth_top/wishbone/select_347/sel[21] (select_347) n933
8.979 0.957 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f eth_top/wishbone/select_347/o[0] (select_347) n1020
9.799 0.820 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f eth_top/wishbone/tx_burst_cnt_38/d[0] (tx_burst_cnt_38) n1020
9.799 data arrival time
9.799 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
8.112 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
8.112 data required time
9.799 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-1.687 slack (VIOLATED)
Item: 2
Path ID: 2
Startpoint: wb1_we_i (in port)
Endpoint: wb_conmax_top/m2/s1_cyc_o_1/d (s1_cyc_o_1) s1_cyc_o_next
Path Type: max
Constraint: en gated clock setup
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& f wb1_we_i (in) wb1_we_i
0.688 0.688 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/wb1_we_i (wb_dma_top) wb1_we_i
1.415 0.727 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/wb_we_i (u4) wb1_we_i
2.016 0.601 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/wb_we_i (u1) wb_we_i
2.032 0.016 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/buf_6/i[2] (buf_6) wb_we_i
2.432 0.400 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/buf_6/o[0] (buf_6) slv_pt_out[0]
2.455 0.023 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/slv_pt_out[0] (u1) slv_pt_out[0]
2.718 0.262 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/slv_pt_out[0] (u4) slv1_pt_out[0]
3.136 0.419 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/buf_15/i[0] (buf_15) slv1_pt_out[0]
3.735 0.598 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/buf_15/o[0] (buf_15) mast0_pt_in[0]
3.803 0.069 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/mast_pt_in[0] (u3) mast0_pt_in[0]
4.561 0.758 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u0/mast_pt_in[0] (u0) mast_pt_in[0]
4.822 0.260 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u0/mux_3/d1[0] (mux_3) mast_pt_in[0]
5.506 0.685 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/mux_3/o[1] (mux_3) wb_cyc_o
6.254 0.747 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/wb_cyc_o (u0) wb_cyc_o
6.542 0.288 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/wb_cyc_o (u3) wb0_cyc_o
6.969 0.428 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb0_cyc_o (wb_dma_top) m2_cyc_i
7.578 0.609 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2_cyc_i (wb_conmax_top) m2_cyc_i
8.191 0.612 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/wb_cyc_i (m2) m2_cyc_i
8.286 0.095 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/i78/d1 (i78) wb_cyc_i
8.932 0.646 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/i78/o (i78) n1202
9.827 0.895 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/i79/d0 (i79) n1202
9.878 0.050 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/i79/o (i79) s1_cyc_o_next
10.708 0.831 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/s1_cyc_o_1/d (s1_cyc_o_1) s1_cyc_o_next
10.708 data arrival time
10.708 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
8.602 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
8.602 data required time
10.708 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-2.106 slack (VIOLATED)
Item: 3
Path ID: 3
Startpoint: spoci_sda_i (in port)
Endpoint: pci_bridge32/configuration/i_pci_spoci_ctrl/sda_i_reg_3/d (sda_i_reg_3) n40
Path Type: max
Constraint: en gated clock setup
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& r spoci_sda_i (in) spoci_sda_i
0.209 0.209 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/spoci_sda_i (pci_bridge32) spoci_sda_i
0.867 0.658 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/configuration/spoci_sda_i (configuration) spoci_sda_i
1.478 0.611 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/configuration/i_pci_spoci_ctrl/pci_spoci_sda_i (i_pci_spoci_ctrl) spoci_sda_i
2.152 0.674 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/configuration/i_pci_spoci_ctrl/i12/d1 (i12) pci_spoci_sda_i
3.104 0.952 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/configuration/i_pci_spoci_ctrl/i12/o (i12) n40
3.231 0.127 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/configuration/i_pci_spoci_ctrl/sda_i_reg_3/d (sda_i_reg_3) n40
3.231 data arrival time
3.231 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
5.394 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
5.394 data required time
3.231 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2.163 slack (MET)
Item: 4
Path ID: 4
Startpoint: wb1_ack_i (in port)
Endpoint: wb_dma_top/u4/u0/mast_dout_5/d[6] (mast_dout_5) n139
Path Type: max
Constraint: en gated clock setup
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& f wb1_ack_i (in) wb1_ack_i
0.845 0.845 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/wb1_ack_i (wb_dma_top) wb1_ack_i
1.803 0.958 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/wb_ack_i (u4) wb1_ack_i
2.181 0.378 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u0/wb_ack_i (u0) wb_ack_i
3.074 0.893 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u0/mux_6/sel (mux_6) wb_ack_i
3.144 0.070 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u0/mux_6/o[6] (mux_6) n139
3.381 0.237 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u0/mast_dout_5/d[6] (mast_dout_5) n139
3.381 data arrival time
3.381 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
6.740 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
6.740 data required time
3.381 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
3.358 slack (MET)
Item: 5
Path ID: 5
Startpoint: pci_par_i (in port)
Endpoint: pci_bridge32/output_backup/perr_en_out_12/d (perr_en_out_12) perr_en_in
Path Type: max
Constraint: en gated clock setup
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& f pci_par_i (in) pci_par_i
0.097 0.097 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_par_i (pci_bridge32) pci_par_i
0.389 0.292 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/i54/d0 (i54) pci_par_i
0.816 0.427 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/i54/o (i54) int_pci_par
0.886 0.070 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/i242/i (i242) int_pci_par
1.691 0.805 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/i242/o (i242) parchk_pci_par_in
2.284 0.592 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/parity_checker/pci_par_in (parity_checker) parchk_pci_par_in
2.706 0.422 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/parity_checker/perr_en_crit_gen/pci_par_in (perr_en_crit_gen) pci_par_in
2.865 0.159 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/parity_checker/perr_en_crit_gen/i5/a1 (i5) pci_par_in
3.346 0.482 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/parity_checker/perr_en_crit_gen/i5/o (i5) n5
4.181 0.834 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/parity_checker/perr_en_crit_gen/i6/a1 (i6) n5
4.321 0.140 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/parity_checker/perr_en_crit_gen/i6/o (i6) perr
4.978 0.657 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/parity_checker/perr_en_crit_gen/i9/a0 (i9) perr
5.336 0.358 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/parity_checker/perr_en_crit_gen/i9/o (i9) perr_en_out
5.510 0.175 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/parity_checker/perr_en_crit_gen/perr_en_out (perr_en_crit_gen) pci_perr_en_out
6.382 0.871 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/parity_checker/pci_perr_en_out (parity_checker) parchk_pci_perr_en_out
6.488 0.106 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/i232/i (i232) parchk_pci_perr_en_out
6.601 0.113 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/i232/o (i232) pci_mux_perr_en_in
7.440 0.840 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/output_backup/perr_en_in (output_backup) pci_mux_perr_en_in
7.881 0.441 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/output_backup/perr_en_out_12/d (perr_en_out_12) perr_en_in
7.881 data arrival time
7.881 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
1.315 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1.315 data required time
7.881 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-6.567 slack (VIOLATED)
Item: 6
Path ID: 6
Startpoint: intrq_pad_i (in port)
Endpoint: atahost_top/u1/cINTRQ_1/d (cINTRQ_1) INTRQ
Path Type: max
Constraint: en gated clock setup
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& r intrq_pad_i (in) intrq_pad_i
0.440 0.440 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r atahost_top/intrq_pad_i (atahost_top) intrq_pad_i
1.000 0.560 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r atahost_top/u1/INTRQ (u1) intrq_pad_i
1.087 0.087 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r atahost_top/u1/cINTRQ_1/d (cINTRQ_1) INTRQ
1.087 data arrival time
1.087 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
2.172 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2.172 data required time
1.087 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1.084 slack (MET)
Item: 7
Path ID: 7
Startpoint: dbg_we_i (in port)
Endpoint: or1200_top/or1200_du/dmr1_3/d[5] (dmr1_3) n262
Path Type: max
Constraint: en gated clock setup
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& r dbg_we_i (in) dbg_we_i
0.850 0.850 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/dbg_we_i (or1200_top) dbg_we_i
1.302 0.452 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_du/dbg_we_i (or1200_du) dbg_we_i
2.281 0.979 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_du/i21/a1 (i21) dbg_we_i
2.709 0.428 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_du/i21/o (i21) du_write
3.569 0.859 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_du/du_write (or1200_du) du_write
3.645 0.076 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_cpu/du_write (or1200_cpu) du_write
3.716 0.071 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_cpu/or1200_sprs/du_write (or1200_sprs) du_write
4.118 0.402 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_cpu/or1200_sprs/mux_8/sel (mux_8) du_write
4.748 0.630 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_cpu/or1200_sprs/mux_8/o[0] (mux_8) spr_dat_o[0]
4.871 0.123 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_cpu/or1200_sprs/spr_dat_o[0] (or1200_sprs) spr_dat_cpu[0]
4.982 0.111 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_cpu/spr_dat_cpu[0] (or1200_cpu) spr_dat_cpu[0]
5.389 0.408 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_du/spr_dat_i[0] (or1200_du) spr_dat_cpu[0]
6.006 0.617 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_du/mux_124/d1[0] (mux_124) spr_dat_i[0]
6.532 0.526 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_du/mux_124/o[5] (mux_124) n262
7.215 0.683 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_du/dmr1_3/d[5] (dmr1_3) n262
7.215 data arrival time
7.215 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
12.135 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
12.135 data required time
7.215 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
4.920 slack (MET)
Item: 8
Path ID: 8
Startpoint: s5_rty_i (in port)
Endpoint: pci_bridge32/pci_target_unit/wishbone_master/rty_counter_4/d[0] (rty_counter_4) n85
Path Type: max
Constraint: en gated clock setup
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& r s5_rty_i (in) s5_rty_i
0.332 0.332 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s5_rty_i (wb_conmax_top) s5_rty_i
0.430 0.097 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s5/wb_rty_i (s5) s5_rty_i
1.291 0.861 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s5/i87/a1 (i87) wb_rty_i
1.672 0.381 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s5/i87/o (i87) m4_rty_o
2.592 0.920 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s5/m4_rty_o (s5) m4s5_rty
3.304 0.712 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m4/s5_rty_i (m4) m4s5_rty
3.488 0.184 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m4/Mux_215/data[5] (Mux_215) s5_rty_i
3.818 0.330 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m4/Mux_215/o (Mux_215) wb_rty_o
4.478 0.660 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m4/wb_rty_o (m4) m4_rty_o
4.662 0.183 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m4_rty_o (wb_conmax_top) m4_rty_o
4.781 0.120 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/wbm_rty_i (pci_bridge32) m4_rty_o
5.568 0.787 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/i131/i (i131) wbm_rty_i
6.270 0.701 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/i131/o (i131) pciu_rty_in
6.921 0.652 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/pci_target_unit/pciu_wbm_rty_i (pci_target_unit) pciu_rty_in
7.535 0.613 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/pci_target_unit/i52/i (i52) pciu_wbm_rty_i
7.933 0.398 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/pci_target_unit/i52/o (i52) wbm_sm_rty_in
8.677 0.744 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/pci_target_unit/wishbone_master/wb_rty_i (wishbone_master) wbm_sm_rty_in
9.363 0.686 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r pci_bridge32/pci_target_unit/wishbone_master/i44/a0 (i44) wb_rty_i
10.099 0.736 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_target_unit/wishbone_master/i44/o (i44) retry
10.483 0.385 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_target_unit/wishbone_master/mux_49/sel (mux_49) retry
10.702 0.219 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_target_unit/wishbone_master/mux_49/o[0] (mux_49) n76
11.064 0.361 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_target_unit/wishbone_master/mux_50/d0[0] (mux_50) n76
11.936 0.873 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_target_unit/wishbone_master/mux_50/o[0] (mux_50) n85
12.185 0.249 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_target_unit/wishbone_master/rty_counter_4/d[0] (rty_counter_4) n85
12.185 data arrival time
12.185 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
18.793 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
18.793 data required time
12.185 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
6.608 slack (MET)
Item: 9
Path ID: 9
Startpoint: dbg_ewt_i (in port)
Endpoint: or1200_top/or1200_du/dwcr0_23/d[4] (dwcr0_23) n1193
Path Type: max
Constraint: en gated clock setup
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& r dbg_ewt_i (in) dbg_ewt_i
0.600 0.600 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/dbg_ewt_i (or1200_top) dbg_ewt_i
1.528 0.927 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_du/dbg_ewt_i (or1200_du) dbg_ewt_i
1.849 0.321 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_du/Mux_529/data[0] (Mux_529) dbg_ewt_i
2.409 0.560 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_du/Mux_529/o (Mux_529) wp[10]
2.865 0.456 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_du/and_511/a[10] (and_511) wp[10]
3.098 0.232 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_du/and_511/o[0] (and_511) n2179
3.816 0.719 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_du/reduce_or_512/a[0] (reduce_or_512) n2179
4.751 0.935 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_du/reduce_or_512/o (reduce_or_512) n2180
4.860 0.109 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_du/i514/d1 (i514) n2180
4.912 0.051 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_du/i514/o (i514) incr_wpcntr0
5.315 0.404 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_du/mux_573/sel (mux_573) incr_wpcntr0
6.125 0.810 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_du/mux_573/o[0] (mux_573) n1164
6.726 0.601 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r or1200_top/or1200_du/mux_222/d0[0] (mux_222) n1164
7.504 0.778 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_du/mux_222/o[4] (mux_222) n1193
7.512 0.008 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f or1200_top/or1200_du/dwcr0_23/d[4] (dwcr0_23) n1193
7.512 data arrival time
7.512 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
8.099 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
8.099 data required time
7.512 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0.587 slack (MET)
Item: 10
Path ID: 10
Startpoint: wb1_rty_i (in port)
Endpoint: ac97_top/u12/dout_17/d[7] (dout_17) wb_data_i[7]
Path Type: max
Constraint: en gated clock setup
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& f wb1_rty_i (in) wb1_rty_i
0.629 0.629 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/wb1_rty_i (wb_dma_top) wb1_rty_i
1.402 0.773 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/wb_rty_i (u4) wb1_rty_i
1.768 0.366 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u0/wb_rty_i (u0) wb_rty_i
2.481 0.714 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u0/buf_4/i[0] (buf_4) wb_rty_i
2.565 0.084 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u0/buf_4/o[0] (buf_4) mast_pt_out[0]
2.788 0.223 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u0/mast_pt_out[0] (u0) mast_pt_out[0]
3.525 0.737 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/mast_pt_out[0] (u4) mast1_pt_out[0]
3.857 0.332 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/buf_14/i[0] (buf_14) mast1_pt_out[0]
4.107 0.250 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/buf_14/o[0] (buf_14) slv0_pt_in[0]
4.996 0.889 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/slv_pt_in[0] (u3) slv0_pt_in[0]
5.883 0.887 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u1/slv_pt_in[0] (u1) slv_pt_in[0]
6.692 0.809 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u1/mux_7/d1[0] (mux_7) slv_pt_in[0]
6.913 0.221 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u1/mux_7/o[3] (mux_7) wb_data_o[0]
6.961 0.048 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u1/wb_data_o[0] (u1) wbm_data_o[0]
7.198 0.236 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/wbm_data_o[0] (u3) wb0m_data_o[0]
7.419 0.221 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/wb0m_data_o[0] (wb_dma_top) m2_data_i[0]
8.049 0.631 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2_data_i[0] (wb_conmax_top) m2_data_i[0]
8.823 0.774 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/wb_data_i[0] (m2) m2_data_i[0]
9.538 0.714 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/buf_41/i[0] (buf_41) wb_data_i[0]
9.587 0.050 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/buf_41/o[0] (buf_41) s5_data_o[0]
9.614 0.027 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/s5_data_o[0] (m2) m2s5_data_o[0]
10.380 0.766 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s5/m2_data_i[0] (s5) m2s5_data_o[0]
10.624 0.244 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s5/mux_9/data2[0] (mux_9) m2_data_i[0]
10.778 0.154 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s5/mux_9/o[7] (mux_9) wb_data_o[7]
11.101 0.323 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s5/wb_data_o[7] (s5) s5_data_o[7]
11.148 0.047 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s5_data_o[7] (wb_conmax_top) s5_data_o[7]
11.773 0.625 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/wb_data_i[7] (ac97_top) s5_data_o[7]
12.483 0.710 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u12/wb_data_i[7] (u12) wb_data_i[7]
12.865 0.382 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u12/dout_17/d[7] (dout_17) wb_data_i[7]
12.865 data arrival time
12.865 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
0.198 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0.198 data required time
12.865 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-12.666 slack (VIOLATED)
Item: 11
Path ID: 11
Startpoint: pci_clk_i (in port)
Endpoint: pci_ad_o[4] (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& f pci_clk_i (in) pci_clk_i
0.696 0.696 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_clk_i (pci_bridge32) pci_clk_i
1.077 0.381 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/i9/i (i9) pci_clk_i
1.507 0.430 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/i9/o (i9) pci_clk
1.564 0.057 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/pci_clock_in (wishbone_slave_unit) pci_clk
2.114 0.551 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/fifos/pci_clock_in (fifos) pci_clock_in
2.575 0.461 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_storage/clk_b (wbw_fifo_storage) pci_clock_in
3.151 0.575 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_storage/do_reg_b_1/clk (do_reg_b_1) clk_b
3.600 0.449 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_storage/do_reg_b_1/q[0] (do_reg_b_1) do_reg_b[0]
3.782 0.182 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_storage/buf_4/i[0] (buf_4) do_reg_b[0]
3.982 0.201 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_storage/buf_4/o[0] (buf_4) do_b[0]
4.727 0.745 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/fifos/wbw_fifo_storage/do_b[0] (wbw_fifo_storage) dpram_portB_output[0]
5.514 0.787 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/fifos/buf_15/i[0] (buf_15) dpram_portB_output[0]
6.276 0.762 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/fifos/buf_15/o[0] (buf_15) wbw_addr_data_out[0]
6.643 0.367 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/fifos/wbw_addr_data_out[0] (fifos) fifos_wbw_addr_data_out[0]
6.697 0.054 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/buf_111/i[0] (buf_111) fifos_wbw_addr_data_out[0]
7.204 0.507 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/buf_111/o[0] (buf_111) pcim_if_wbw_addr_data_in[0]
8.036 0.832 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/pci_initiator_if/wbw_fifo_addr_data_in[0] (pci_initiator_if) pcim_if_wbw_addr_data_in[0]
8.301 0.264 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/pci_initiator_if/mux_191/d1[0] (mux_191) wbw_fifo_addr_data_in[0]
8.674 0.373 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/pci_initiator_if/mux_191/o[0] (mux_191) next_data_out[0]
8.761 0.087 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/pci_initiator_if/next_data_out[0] (pci_initiator_if) pcim_if_next_data_out[0]
9.008 0.247 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/buf_147/i[0] (buf_147) pcim_if_next_data_out[0]
9.550 0.542 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/buf_147/o[0] (buf_147) pcim_sm_next_data_in[0]
9.800 0.250 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/pci_initiator_sm/next_data_in[0] (pci_initiator_sm) pcim_sm_next_data_in[0]
10.437 0.637 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/pci_initiator_sm/mux_159/data2[0] (mux_159) next_data_in[0]
10.682 0.244 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/pci_initiator_sm/mux_159/o[0] (mux_159) pci_ad_out[0]
10.929 0.247 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/pci_initiator_sm/pci_ad_out[0] (pci_initiator_sm) pcim_sm_ad_out[0]
11.168 0.240 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/buf_17/i[0] (buf_17) pcim_sm_ad_out[0]
11.976 0.808 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/buf_17/o[0] (buf_17) wbu_pciif_ad_out[0]
12.772 0.796 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/wishbone_slave_unit/wbu_pciif_ad_out[0] (wishbone_slave_unit) wbu_pciif_ad_out[0]
13.091 0.319 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/buf_219/i[0] (buf_219) wbu_pciif_ad_out[0]
14.078 0.986 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/buf_219/o[0] (buf_219) pci_mux_mas_ad_in[0]
14.628 0.550 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_io_mux/mas_ad_in[0] (pci_io_mux) pci_mux_mas_ad_in[0]
14.659 0.031 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_io_mux/mux_3/d0[0] (mux_3) mas_ad_in[0]
15.397 0.737 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_io_mux/mux_3/o[0] (mux_3) temp_ad[0]
15.551 0.154 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_io_mux/ad_iob0/dat_in (ad_iob0) temp_ad[0]
15.650 0.100 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_io_mux/ad_iob0/i6/d1 (i6) dat_in
15.725 0.074 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_io_mux/ad_iob0/i6/o (i6) n6
15.822 0.097 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_io_mux/ad_iob0/dat_out_1/d (dat_out_1) n6
16.493 0.671 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_io_mux/ad_iob0/dat_out_1/q (dat_out_1) dat_out
16.988 0.495 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_io_mux/ad_iob0/dat_out (ad_iob0) ad_out[0]
17.604 0.615 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_io_mux/ad_out[0] (pci_io_mux) pci_mux_ad_out[0]
18.261 0.657 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/buf_43/i[0] (buf_43) pci_mux_ad_out[0]
19.249 0.988 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/buf_43/o[4] (buf_43) pci_ad_o[4]
19.476 0.227 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_bridge32/pci_ad_o[4] (pci_bridge32) pci_ad_o[4]
19.947 0.471 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f pci_ad_o[4] (out) pci_ad_o[4]
19.947 data arrival time
19.947 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
28.812 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
28.812 data required time
19.947 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
8.865 slack (MET)
Item: 12
Path ID: 12
Startpoint: s9_rty_i (in port)
Endpoint: wb1_err_o (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& r s9_rty_i (in) s9_rty_i
0.148 0.148 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s9_rty_i (wb_conmax_top) s9_rty_i
0.486 0.339 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s9/wb_rty_i (s9) s9_rty_i
1.297 0.811 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s9/i83/a1 (i83) wb_rty_i
1.302 0.005 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s9/i83/o (i83) m2_rty_o
2.257 0.955 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s9/m2_rty_o (s9) m2s9_rty
2.914 0.657 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/s9_rty_i (m2) m2s9_rty
3.857 0.943 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/Mux_215/data[9] (Mux_215) s9_rty_i
4.803 0.947 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/Mux_215/o (Mux_215) wb_rty_o
5.712 0.908 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/wb_rty_o (m2) m2_rty_o
6.396 0.685 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2_rty_o (wb_conmax_top) m2_rty_o
7.052 0.656 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/wb0_rty_i (wb_dma_top) m2_rty_o
7.405 0.353 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/wb_rty_i (u3) wb0_rty_i
8.097 0.692 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u0/wb_rty_i (u0) wb_rty_i
8.812 0.715 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u0/buf_4/i[0] (buf_4) wb_rty_i
9.740 0.929 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u0/buf_4/o[0] (buf_4) mast_pt_out[0]
10.271 0.531 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u0/mast_pt_out[0] (u0) mast_pt_out[0]
10.392 0.121 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/mast_pt_out[0] (u3) mast0_pt_out[0]
10.396 0.004 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/buf_16/i[0] (buf_16) mast0_pt_out[0]
10.696 0.300 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/buf_16/o[0] (buf_16) slv1_pt_in[0]
10.785 0.089 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/slv_pt_in[0] (u4) slv1_pt_in[0]
11.044 0.259 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/slv_pt_in[0] (u1) slv_pt_in[0]
11.985 0.941 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/mux_7/d1[0] (mux_7) slv_pt_in[0]
12.836 0.850 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/mux_7/o[1] (mux_7) wb_err_o
13.647 0.811 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/wb_err_o (u1) wb_err_o
14.578 0.931 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/wb_err_o (u4) wb1_err_o
15.078 0.500 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/wb1_err_o (wb_dma_top) wb1_err_o
15.368 0.290 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb1_err_o (out) wb1_err_o
15.368 data arrival time
15.368 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
29.043 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
29.043 data required time
15.368 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
13.675 slack (MET)
Item: 13
Path ID: 13
Startpoint: s12_rty_i (in port)
Endpoint: wb1m_data_o[3] (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& f s12_rty_i (in) s12_rty_i
0.059 0.059 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s12_rty_i (wb_conmax_top) s12_rty_i
0.795 0.736 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s12/wb_rty_i (s12) s12_rty_i
1.341 0.547 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s12/i83/a1 (i83) wb_rty_i
1.942 0.601 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s12/i83/o (i83) m2_rty_o
2.641 0.699 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s12/m2_rty_o (s12) m2s12_rty
2.711 0.070 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/s12_rty_i (m2) m2s12_rty
2.890 0.179 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/Mux_215/data[12] (Mux_215) s12_rty_i
3.366 0.476 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/Mux_215/o (Mux_215) wb_rty_o
4.201 0.835 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/wb_rty_o (m2) m2_rty_o
4.825 0.624 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2_rty_o (wb_conmax_top) m2_rty_o
5.034 0.209 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb0_rty_i (wb_dma_top) m2_rty_o
5.684 0.650 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/wb_rty_i (u3) wb0_rty_i
6.381 0.697 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/wb_rty_i (u0) wb_rty_i
7.098 0.717 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/i[0] (buf_4) wb_rty_i
7.528 0.431 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/o[0] (buf_4) mast_pt_out[0]
7.968 0.440 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/mast_pt_out[0] (u0) mast_pt_out[0]
8.753 0.785 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/mast_pt_out[0] (u3) mast0_pt_out[0]
9.292 0.539 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/i[0] (buf_16) mast0_pt_out[0]
9.377 0.085 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/o[0] (buf_16) slv1_pt_in[0]
10.202 0.825 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/slv_pt_in[0] (u4) slv1_pt_in[0]
10.836 0.634 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/slv_pt_in[0] (u1) slv_pt_in[0]
11.541 0.705 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/d1[0] (mux_7) slv_pt_in[0]
11.631 0.090 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/o[6] (mux_7) wb_data_o[3]
11.858 0.226 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/wb_data_o[3] (u1) wbm_data_o[3]
12.276 0.418 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/wbm_data_o[3] (u4) wb1m_data_o[3]
12.987 0.711 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb1m_data_o[3] (wb_dma_top) wb1m_data_o[3]
13.031 0.044 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb1m_data_o[3] (out) wb1m_data_o[3]
13.031 data arrival time
13.031 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
24.136 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
24.136 data required time
13.031 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
11.106 slack (MET)
Item: 14
Path ID: 14
Startpoint: s10_rty_i (in port)
Endpoint: wb1_ack_o (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& f s10_rty_i (in) s10_rty_i
0.267 0.267 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s10_rty_i (wb_conmax_top) s10_rty_i
0.477 0.210 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s10/wb_rty_i (s10) s10_rty_i
0.790 0.313 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s10/i83/a1 (i83) wb_rty_i
0.802 0.012 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s10/i83/o (i83) m2_rty_o
1.795 0.993 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s10/m2_rty_o (s10) m2s10_rty
1.860 0.065 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/s10_rty_i (m2) m2s10_rty
2.228 0.368 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/Mux_215/data[10] (Mux_215) s10_rty_i
3.043 0.815 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/Mux_215/o (Mux_215) wb_rty_o
3.951 0.907 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/wb_rty_o (m2) m2_rty_o
4.238 0.287 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2_rty_o (wb_conmax_top) m2_rty_o
4.398 0.161 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb0_rty_i (wb_dma_top) m2_rty_o
5.024 0.626 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/wb_rty_i (u3) wb0_rty_i
5.621 0.597 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/wb_rty_i (u0) wb_rty_i
5.663 0.042 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/i[0] (buf_4) wb_rty_i
6.462 0.799 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/o[0] (buf_4) mast_pt_out[0]
7.065 0.603 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/mast_pt_out[0] (u0) mast_pt_out[0]
7.689 0.624 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/mast_pt_out[0] (u3) mast0_pt_out[0]
8.100 0.412 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/i[0] (buf_16) mast0_pt_out[0]
8.741 0.641 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/o[0] (buf_16) slv1_pt_in[0]
8.783 0.042 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/slv_pt_in[0] (u4) slv1_pt_in[0]
9.008 0.226 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/slv_pt_in[0] (u1) slv_pt_in[0]
9.911 0.902 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/d1[0] (mux_7) slv_pt_in[0]
10.267 0.356 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/o[2] (mux_7) wb_ack_o
10.396 0.129 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/wb_ack_o (u1) wb_ack_o
10.585 0.188 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/wb_ack_o (u4) wb1_ack_o
11.307 0.722 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb1_ack_o (wb_dma_top) wb1_ack_o
11.312 0.006 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb1_ack_o (out) wb1_ack_o
11.312 data arrival time
11.312 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
21.299 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
21.299 data required time
11.312 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
9.987 slack (MET)
Item: 15
Path ID: 15
Startpoint: s8_rty_i (in port)
Endpoint: wb1m_data_o[2] (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& r s8_rty_i (in) s8_rty_i
0.827 0.827 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s8_rty_i (wb_conmax_top) s8_rty_i
1.128 0.301 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s8/wb_rty_i (s8) s8_rty_i
2.093 0.965 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s8/i83/a1 (i83) wb_rty_i
2.968 0.875 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s8/i83/o (i83) m2_rty_o
3.967 0.999 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s8/m2_rty_o (s8) m2s8_rty
4.813 0.846 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/s8_rty_i (m2) m2s8_rty
5.721 0.908 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/Mux_215/data[8] (Mux_215) s8_rty_i
5.849 0.128 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/Mux_215/o (Mux_215) wb_rty_o
6.396 0.548 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/wb_rty_o (m2) m2_rty_o
7.136 0.740 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2_rty_o (wb_conmax_top) m2_rty_o
7.290 0.154 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb0_rty_i (wb_dma_top) m2_rty_o
7.878 0.588 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/wb_rty_i (u3) wb0_rty_i
8.544 0.666 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/wb_rty_i (u0) wb_rty_i
9.467 0.923 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/i[0] (buf_4) wb_rty_i
9.649 0.181 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/o[0] (buf_4) mast_pt_out[0]
9.908 0.259 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/mast_pt_out[0] (u0) mast_pt_out[0]
10.402 0.494 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/mast_pt_out[0] (u3) mast0_pt_out[0]
10.611 0.208 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/i[0] (buf_16) mast0_pt_out[0]
10.820 0.209 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/o[0] (buf_16) slv1_pt_in[0]
11.185 0.365 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/slv_pt_in[0] (u4) slv1_pt_in[0]
11.923 0.738 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/slv_pt_in[0] (u1) slv_pt_in[0]
11.965 0.043 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/d1[0] (mux_7) slv_pt_in[0]
12.040 0.074 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/o[5] (mux_7) wb_data_o[2]
12.651 0.612 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/wb_data_o[2] (u1) wbm_data_o[2]
12.865 0.214 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/wbm_data_o[2] (u4) wb1m_data_o[2]
13.413 0.547 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb1m_data_o[2] (wb_dma_top) wb1m_data_o[2]
14.036 0.623 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb1m_data_o[2] (out) wb1m_data_o[2]
14.036 data arrival time
14.036 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
0.896 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0.896 data required time
14.036 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-13.140 slack (VIOLATED)
Item: 16
Path ID: 16
Startpoint: bit_clk_pad_i (in port)
Endpoint: sdata_pad_o (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& f bit_clk_pad_i (in) bit_clk_pad_i
0.089 0.089 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/bit_clk_pad_i (ac97_top) bit_clk_pad_i
1.011 0.922 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u0/clk (u0) bit_clk_pad_i
1.612 0.602 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u0/slt1_r_1/clk (slt1_r_1) clk
2.037 0.425 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u0/slt1_r_1/q[19] (slt1_r_1) slt1_r[19]
2.203 0.166 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u0/mux_5/d0[0] (mux_5) slt1_r[19]
2.401 0.198 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u0/mux_5/o[3] (mux_5) n19
2.943 0.542 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u0/slt0_r_13/d[3] (slt0_r_13) n19
3.379 0.436 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u0/slt0_r_13/q[15] (slt0_r_13) slt0_r[15]
3.942 0.563 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u0/i4/i (i4) slt0_r[15]
4.246 0.305 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u0/i4/o (i4) sdata_out
4.679 0.433 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/u0/sdata_out (u0) sdata_pad_o
5.327 0.647 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f ac97_top/sdata_pad_o (ac97_top) sdata_pad_o
6.022 0.696 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f sdata_pad_o (out) sdata_pad_o
6.022 data arrival time
6.022 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
8.653 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
8.653 data required time
6.022 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2.631 slack (MET)
Item: 17
Path ID: 17
Startpoint: s9_rty_i (in port)
Endpoint: wb1_rty_o (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& r s9_rty_i (in) s9_rty_i
0.187 0.187 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s9_rty_i (wb_conmax_top) s9_rty_i
0.853 0.667 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s9/wb_rty_i (s9) s9_rty_i
1.760 0.907 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s9/i83/a1 (i83) wb_rty_i
2.511 0.750 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s9/i83/o (i83) m2_rty_o
2.690 0.179 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s9/m2_rty_o (s9) m2s9_rty
3.563 0.873 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/s9_rty_i (m2) m2s9_rty
4.268 0.705 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/Mux_215/data[9] (Mux_215) s9_rty_i
4.816 0.548 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/Mux_215/o (Mux_215) wb_rty_o
5.091 0.275 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/wb_rty_o (m2) m2_rty_o
5.784 0.693 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2_rty_o (wb_conmax_top) m2_rty_o
6.365 0.581 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb0_rty_i (wb_dma_top) m2_rty_o
6.702 0.337 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/wb_rty_i (u3) wb0_rty_i
7.651 0.949 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/wb_rty_i (u0) wb_rty_i
7.942 0.291 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/i[0] (buf_4) wb_rty_i
8.020 0.077 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/o[0] (buf_4) mast_pt_out[0]
8.537 0.517 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/mast_pt_out[0] (u0) mast_pt_out[0]
8.752 0.215 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/mast_pt_out[0] (u3) mast0_pt_out[0]
9.648 0.895 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/i[0] (buf_16) mast0_pt_out[0]
9.878 0.231 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/o[0] (buf_16) slv1_pt_in[0]
9.895 0.017 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/slv_pt_in[0] (u4) slv1_pt_in[0]
10.618 0.724 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/slv_pt_in[0] (u1) slv_pt_in[0]
10.684 0.066 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/d1[0] (mux_7) slv_pt_in[0]
11.170 0.486 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/o[0] (mux_7) wb_rty_o
12.130 0.959 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/wb_rty_o (u1) wb_rty_o
13.129 1.000 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/wb_rty_o (u4) wb1_rty_o
13.593 0.464 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb1_rty_o (wb_dma_top) wb1_rty_o
14.381 0.788 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb1_rty_o (out) wb1_rty_o
14.381 data arrival time
14.381 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
25.045 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
25.045 data required time
14.381 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.664 slack (MET)
Item: 18
Path ID: 18
Startpoint: s15_rty_i (in port)
Endpoint: wb1_ack_o (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& r s15_rty_i (in) s15_rty_i
0.831 0.831 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s15_rty_i (wb_conmax_top) s15_rty_i
0.898 0.067 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/rf/e_wb_rty_i (rf) s15_rty_i
1.827 0.929 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/rf/i110/d0 (i110) e_wb_rty_i
2.734 0.908 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/rf/i110/o (i110) i_wb_rty_o
3.311 0.576 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/rf/i_wb_rty_o (rf) i_s15_rty_i
3.677 0.366 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s15/wb_rty_i (s15) i_s15_rty_i
4.060 0.384 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s15/i83/a1 (i83) wb_rty_i
4.718 0.658 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s15/i83/o (i83) m2_rty_o
5.211 0.493 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s15/m2_rty_o (s15) m2s15_rty
5.897 0.686 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/s15_rty_i (m2) m2s15_rty
6.670 0.773 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/Mux_215/data[15] (Mux_215) s15_rty_i
7.517 0.846 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/Mux_215/o (Mux_215) wb_rty_o
8.346 0.829 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/wb_rty_o (m2) m2_rty_o
8.361 0.015 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2_rty_o (wb_conmax_top) m2_rty_o
9.185 0.825 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/wb0_rty_i (wb_dma_top) m2_rty_o
9.823 0.637 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/wb_rty_i (u3) wb0_rty_i
10.643 0.820 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u0/wb_rty_i (u0) wb_rty_i
11.071 0.427 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u0/buf_4/i[0] (buf_4) wb_rty_i
11.399 0.328 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u0/buf_4/o[0] (buf_4) mast_pt_out[0]
11.637 0.238 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/u0/mast_pt_out[0] (u0) mast_pt_out[0]
12.533 0.896 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u3/mast_pt_out[0] (u3) mast0_pt_out[0]
12.539 0.007 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/buf_16/i[0] (buf_16) mast0_pt_out[0]
12.901 0.361 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/buf_16/o[0] (buf_16) slv1_pt_in[0]
13.061 0.160 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/slv_pt_in[0] (u4) slv1_pt_in[0]
13.251 0.191 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/slv_pt_in[0] (u1) slv_pt_in[0]
13.434 0.183 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/mux_7/d1[0] (mux_7) slv_pt_in[0]
14.216 0.782 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/mux_7/o[2] (mux_7) wb_ack_o
14.497 0.281 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/wb_ack_o (u1) wb_ack_o
14.842 0.345 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/wb_ack_o (u4) wb1_ack_o
15.264 0.422 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/wb1_ack_o (wb_dma_top) wb1_ack_o
16.049 0.786 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb1_ack_o (out) wb1_ack_o
16.049 data arrival time
16.049 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
28.219 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
28.219 data required time
16.049 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
12.170 slack (MET)
Item: 19
Path ID: 19
Startpoint: s15_rty_i (in port)
Endpoint: wb1m_data_o[2] (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& r s15_rty_i (in) s15_rty_i
0.454 0.454 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s15_rty_i (wb_conmax_top) s15_rty_i
0.853 0.399 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/rf/e_wb_rty_i (rf) s15_rty_i
1.721 0.868 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/rf/i110/d0 (i110) e_wb_rty_i
1.952 0.231 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/rf/i110/o (i110) i_wb_rty_o
2.580 0.628 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/rf/i_wb_rty_o (rf) i_s15_rty_i
2.586 0.006 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s15/wb_rty_i (s15) i_s15_rty_i
3.308 0.723 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s15/i83/a1 (i83) wb_rty_i
3.969 0.661 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s15/i83/o (i83) m2_rty_o
4.927 0.958 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s15/m2_rty_o (s15) m2s15_rty
5.692 0.764 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/s15_rty_i (m2) m2s15_rty
6.252 0.560 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/Mux_215/data[15] (Mux_215) s15_rty_i
7.121 0.869 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/Mux_215/o (Mux_215) wb_rty_o
7.994 0.874 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/wb_rty_o (m2) m2_rty_o
8.608 0.614 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2_rty_o (wb_conmax_top) m2_rty_o
9.164 0.555 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb0_rty_i (wb_dma_top) m2_rty_o
9.788 0.625 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/wb_rty_i (u3) wb0_rty_i
9.991 0.203 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/wb_rty_i (u0) wb_rty_i
10.747 0.756 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/i[0] (buf_4) wb_rty_i
11.204 0.457 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/o[0] (buf_4) mast_pt_out[0]
12.067 0.863 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/mast_pt_out[0] (u0) mast_pt_out[0]
12.172 0.105 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/mast_pt_out[0] (u3) mast0_pt_out[0]
12.385 0.213 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/i[0] (buf_16) mast0_pt_out[0]
13.293 0.908 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/o[0] (buf_16) slv1_pt_in[0]
13.980 0.687 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/slv_pt_in[0] (u4) slv1_pt_in[0]
14.053 0.073 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/slv_pt_in[0] (u1) slv_pt_in[0]
14.992 0.940 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/d1[0] (mux_7) slv_pt_in[0]
15.653 0.661 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/o[5] (mux_7) wb_data_o[2]
15.819 0.166 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/u1/wb_data_o[2] (u1) wbm_data_o[2]
16.040 0.221 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/u4/wbm_data_o[2] (u4) wb1m_data_o[2]
16.843 0.803 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_dma_top/wb1m_data_o[2] (wb_dma_top) wb1m_data_o[2]
17.343 0.500 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb1m_data_o[2] (out) wb1m_data_o[2]
17.343 data arrival time
17.343 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
7.380 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
7.380 data required time
17.343 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-9.963 slack (VIOLATED)
Item: 20
Path ID: 20
Startpoint: s14_rty_i (in port)
Endpoint: wb1_err_o (out port)
Path Type: max
Constraint: set_output_delay check
Wire Coeff Coeff Xtalk Rail Final
Path Incr Adjust Delay adj ratio Delta Trans FTrans Voltage Voltage Cap NT Point Net
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- ---- -- ------------------------------ ------------------------------
0.000 clock CLK (rise)
0.000 input external delay
0.000 0.000 0.140 0.175 0.035 D& r s14_rty_i (in) s14_rty_i
0.750 0.750 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s14_rty_i (wb_conmax_top) s14_rty_i
1.074 0.324 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s14/wb_rty_i (s14) s14_rty_i
1.261 0.187 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/s14/i83/a1 (i83) wb_rty_i
1.519 0.258 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s14/i83/o (i83) m2_rty_o
2.021 0.502 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/s14/m2_rty_o (s14) m2s14_rty
2.863 0.842 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/s14_rty_i (m2) m2s14_rty
3.220 0.357 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & f wb_conmax_top/m2/Mux_215/data[14] (Mux_215) s14_rty_i
4.033 0.813 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/Mux_215/o (Mux_215) wb_rty_o
4.404 0.371 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2/wb_rty_o (m2) m2_rty_o
4.474 0.070 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_conmax_top/m2_rty_o (wb_conmax_top) m2_rty_o
5.120 0.646 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb0_rty_i (wb_dma_top) m2_rty_o
5.635 0.515 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/wb_rty_i (u3) wb0_rty_i
6.391 0.756 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/wb_rty_i (u0) wb_rty_i
6.954 0.563 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/i[0] (buf_4) wb_rty_i
7.779 0.825 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/buf_4/o[0] (buf_4) mast_pt_out[0]
8.269 0.490 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/u0/mast_pt_out[0] (u0) mast_pt_out[0]
8.591 0.322 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u3/mast_pt_out[0] (u3) mast0_pt_out[0]
8.943 0.352 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/i[0] (buf_16) mast0_pt_out[0]
9.491 0.548 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/buf_16/o[0] (buf_16) slv1_pt_in[0]
10.226 0.735 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/slv_pt_in[0] (u4) slv1_pt_in[0]
10.259 0.033 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/slv_pt_in[0] (u1) slv_pt_in[0]
10.892 0.633 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/d1[0] (mux_7) slv_pt_in[0]
11.066 0.174 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/mux_7/o[1] (mux_7) wb_err_o
11.385 0.319 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/u1/wb_err_o (u1) wb_err_o
11.766 0.381 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/u4/wb_err_o (u4) wb1_err_o
12.503 0.737 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb_dma_top/wb1_err_o (wb_dma_top) wb1_err_o
12.900 0.397 0.004 0.000 1.000 0.000 0.140 0.175 0.900 0.900 0.035 & r wb1_err_o (out) wb1_err_o
12.900 data arrival time
12.900 0.000 0.000 Total
0.000 0.000 clock rclk (rise)
0.000 0.000 output external delay
0.000 0.000 clock uncertainty
14.339 data required time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
14.339 data required time
12.900 data arrival time
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1.439 slack (MET)
|