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242 | ###############################################################################
# Copyright (c) 2004-2024 by Altair Engineering, Inc.
# All rights reserved.
#
# Altair Engineering, Inc. makes this software available as part of the Vision
# tool platform. As long as you are a licensee of the Vision tool platform
# you may make copies of the software and modify it to be used within the
# Vision tool platform, but you must include all of this notice on any copy.
# Redistribution without written permission to any third party, with or
# without modification, is not permitted.
# Altair Engineering, Inc. does not warrant that this software is error free
# or fit for any purpose. Altair Engineering, Inc. disclaims any liability for
# all claims, expenses, losses, damages and costs any user may incur as a
# result of using, copying or modifying the software.
# =============================================================================
# @userware
# Create Port- and Netbuses (Pattern Based)
# @section
# Modify the Loaded Database
# @description
# Create portbuses and netbuses from single bit ports and nets.
#
# The script can be used as a template for creating special
# purpose versions. The hard coded pattern for
# collecting simple buses may need modifications.
# Currently the pattern for collecting single bits matches
# simple names like `A[1]`, `B{1}`, `C_1_` or `A1`.
#
# Foreach module all nets are examined. If the name (e.g. `BUS[77]`)
# matches a pattern containing a basename (e.g. `BUS`), some letters
# preceding the bitsubscript (e.g. `[`) and some trailing letters
# (e.g. `]`) this triplet is used as an index identifying the bus.
# All bitsubscripts (e.g. `77`) are collected and sorted in a list.
# After all subscripts are collected, a netBus or portBus is
# created.
# For PortBuses there are no "gaps" in the bitsubscripts allowed.
# If a net is already member of a bus the bitsubscript list is
# cleared to mark the bus as already bundled.
# @files
# makeBuses.tcl
# @example
# demo/spice/gl85.sp
# @cmdline
# -hspice @example[0]
# -userware @files[0]
# @tag
# verilog spice netlist zdb
###############################################################################
# -----------------------------------------------------------------------------
# makeBuses -
# -----------------------------------------------------------------------------
#
proc makeBuses {db} {
##
# Return if the database is empty.
#
if {$db == {}} {
return
}
##
# process all modules
#
$db foreach module mod {
set modName [$db oid oname $mod]
##
# forget old names
#
array unset buses
array unset ports
##
# loop over all nets and ports
#
foreach type {net port} {
$db foreach $type $mod oid {
if {$type=="net"} {
set isDevice 0
$db foreach pin $oid pin {
if {[$db oid type $pin] == "port"} {
continue
}
set i [$db oid convertTo inst $pin]
if {![$db isModule $i]} {
set func [$db primFuncOf $i]
switch -glob $func {
"*DIODE" -
"SWITCH" -
"*MOS" -
"PNP" -
"NPN" -
"CAP" -
"RES" {set isDevice 1}
"UNKNOWN" {}
default {
gui console print \
"Func '$func' not handled."
}
}
}
}
if {$isDevice} {
continue
}
}
set name [$db oid oname $oid]
##
# all bit subscripts of one bus are collected
# in a array indexed by basename and brackets.
# if a net is already member of a bus, the bus
# is marked by an empty list.
#
set matched 0
##
# match busnames like bus_1_, net(1) etc.
#
if {[regexp {^(.+)([\[\(\{\_])([0-9]+)([\]\)\}\_])$} $name \
match base pre bit post]} {
set matched 1
} elseif {[regexp {^([^0-9]+)([0-9]+)$} $name match base bit]} {
set matched 1
set pre {}
set post {}
}
if {$matched} {
if {[regexp {^0[0-9]+$} $bit]} {
continue
}
set idx "$base@$pre@$post"
if {[$db isBusMember $oid]} {
set buses($idx) {} ;# net is already contained in a bus
} elseif {![info exists buses($idx)]||$buses($idx)!={}} {
lappend buses($idx) $bit
if {$type=="port"} {set ports($idx) 1}
}
}
}
}
##
# Loop over all found buses
#
foreach basePrePost [array names buses] {
##
# sort bit subscripts
#
set bits [lsort -integer -unique -decreasing $buses($basePrePost)]
##
# Ignore single bit buses.
#
if {[llength $bits]<=1} {
continue
}
##
# get basename, pre and post brackets
#
set s [split $basePrePost @]
set base [lindex $s 0]
set pre [lindex $s 1]
set post [lindex $s 2]
##
# get msb, lsb and width
#
set msb [lindex $bits 0]
set lsb [lindex $bits end]
set width [expr $msb - $lsb + 1]
##
# modify database
#
$db reloadModule $modName
##
# create list of all sub bits
# for ports we lookup direction at first existing port
#
set isport [info exists ports($basePrePost)]
set portdir {}
set subs {}
for {set bit $msb} {$bit>=$lsb} {incr bit -1} {
set sub "$base$pre$bit$post"
lappend subs $sub
if {$isport && $portdir=={}} {
set p [list port $modName $sub]
if {![catch {$db oid create $p}]} {
set portdir [$db directionOf $p]
}
}
}
set busName "$base$pre$msb:$lsb$post"
eval {$db} load netBus {$busName} {$width} $subs
if {$portdir != {}} {
##
# catch is needed, because new ports can't be created
# if there are 'gaps' in the bus.
#
if {[llength $subs]==$width} {
set ok 1
foreach sub $subs {
set oid [list port $modName $sub]
if {[catch {$db oid create $oid}]} {
set ok 0
zmessage print WAR "Failed to create $oid: $busName"
break
}
}
if {$ok} {
if {[catch {
eval {$db} load portBus {$busName} {$portdir} \
{$width} $subs
} err]} {
zmessage print WAR $err
}
}
}
}
}
}
##
# Update the GUI
#
gui database removeChangedCallback makeBuses
gui database changed $db
}
##
# Use gui database runOrRegisterChangedCallback to immediately run
# makeBuses
# if we have a database, or otherwise register the proc to be executed after
# the database is available.
#
gui database runOrRegisterChangedCallback makeBuses
|