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175 | ###############################################################################
# Copyright (c) 2024 by Altair Engineering, Inc.
# All rights reserved.
#
# Altair Engineering, Inc. makes this software available as part of the Vision
# tool platform. As long as you are a licensee of the Vision tool platform
# you may make copies of the software and modify it to be used within the
# Vision tool platform, but you must include all of this notice on any copy.
# Redistribution without written permission to any third party, with or
# without modification, is not permitted.
# Altair Engineering, Inc. does not warrant that this software is error free
# or fit for any purpose. Altair Engineering, Inc. disclaims any liability for
# all claims, expenses, losses, damages and costs any user may incur as a
# result of using, copying or modifying the software.
# =============================================================================
# @userware
# Import Pcb Netlist
# @section
# Pcb
# @description
# Parse pcb netlist and create ZDB.
#
# Supported formats:
# - siemens / mentor / xpedition
# - altium / protel
# - cadence / orcad
#
# Open issues:
# - symbol / function creation
# - better/unified dict/list handling
# - unified data for one single zdb save code
# - power/ground nets
# - better pin directions
# - sections in orcad (?)
# - error handling
# - insts/primitives checks
#
# Usage:
# *vision -userwareargs pcbimport.tcl \
# "-altium {Altium Netlist.NET}"
# *vision -userwareargs pcbimport.tcl \
# "-siemens {Xpedition Netlist.qcv}"
# *vision -userwareargs pcbimport.tcl \
# "-cadence {OrCAD Netlist Part 1.dat} \
# {OrCAD Netlist Part 2.dat} \
# {OrCAD Netlist Part 3.dat}"
#
# @files
# cust43/pcbsiemens.tcl
# cust43/pcbaltium.tcl
# cust43/pcbcadence.tcl
# @tag
# zdb userware
###############################################################################
source [file join [file dirname [info script]] pcbsiemens.tcl]
source [file join [file dirname [info script]] pcbaltium.tcl]
source [file join [file dirname [info script]] pcbcadence.tcl]
# -----------------------------------------------------------------------------
# pgFlag - map net names to power/ground flag.
# -----------------------------------------------------------------------------
#
proc PcbImport:pgFlag {netName} {
foreach {pattern flag} {
"VDD*" power
"GND*" ground
"[1-9]V*" power
} {
if {[string match $pattern $netName]} {
return $flag
}
}
return {}
}
# -----------------------------------------------------------------------------
# primFunc - map refDes to primitive function.
# -----------------------------------------------------------------------------
#
proc PcbImport:primFunc {refDes} {
foreach {pattern func} {
"C[0-9]*" cap
"R[0-9]*" res
"D[0-9]*" diode
"L[0-9]*" inductor
} {
if {[string match $pattern $refDes]} {
return $func
}
}
return UNKNOWN
}
# =============================================================================
# Init - Call the initialization procedure.
# =============================================================================
#
proc PcbImport:Init {argv} {
if {[llength $argv] == 0} {
puts "[info script] ?-siemens|-altium|-cadence? netlist-files"
exit 1
}
set fnames {}
set type {}
foreach arg $argv {
switch -glob -- $arg {
-siemens {
set type "siemens"
}
-altium {
set type "altium"
}
-cadence {
set type "cadence"
}
-* {
puts "unknown option $arg"
exit 1
}
default {
lappend fnames $arg
}
}
}
if {$fnames == {}} {
puts "netlist filename missing"
exit 1
}
if {$type == {}} {
foreach fname $fnames {
switch -glob -- $fname {
*.qcv {
set type "siemens"
break
}
*.NET {
set type "altium"
break
}
*.dat {
set type "cadence"
break
}
default {
puts "unknown file type for $fname"
exit 1
}
}
}
}
set basename [file rootname [lindex $fnames 0]]
set zdbname $basename.zdb
set topname [file tail $basename]
switch -- $type {
"siemens" {PcbImport:parseQcv $fnames $zdbname $topname}
"altium" {PcbImport:parseAltium $fnames $zdbname $topname}
"cadence" {PcbImport:parseOrcad $fnames $zdbname $topname}
default {}
}
}
##
# start
#
PcbImport:Init $argv
|