1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216 | MODULE SLAVE_CNTRL ;
DESCRIPTION GA13/SLAVE_CNTRL.DETAIL(97) ;
INPUTS
MSTR_REQ_N,DB_AD_LAT-19,STAT_ADDR_N,BIT_16_MODE_N,SLV_REG_DEC_N,RESET,SLV_MEM_DEC_N,CPU_AS
,CPU_BG_N,INT_DSACK-1,INT_DSACK-0,DB_CLK_N,DEV_INH,SW_RES_N,DEV_REQ,INT_ACK
,DB_WR ;
OUTPUTS
SLV_SRC_SEL_N-5,SLV_SRC_SEL_N-4,SLV_SRC_SEL_N-3,SLV_SRC_SEL_N-2,SLV_SRC_SEL_N-1,SLV_SRC_SEL_N-0,EN_SLV_ACK_OUT_N,SLV_WRLAT_ENBL_N
,SLV_ACK_OUT_N,SLV_CYC_DEC_N,TP2-9,TP1-2,TP1-9,TP1-5,SLV_RDLAT_ENBL_N-0,SLV_RDLAT_ENBL_N-1
,SLV_REG_ACC_N,SLV_WR_CYC_N,SLV_AS_N,EN_CPU_DTA_BUS_N-0,EN_CPU_DTA_BUS_N-1,EN_CPU_ADDR_BUS,INT_CPU_BRQ_N,SLV_DRV_DB_N
,BRQ_N,SLV_RD__WR_N,SW_RES_PLS_N,BGACK_N ;
DEFINE
TP2-9 = (SLV_MEM_DEC_N) ;
U1201( U1201.Z = Z)
= NR2( DB_ACTIVE = B, DB_ACTIVE = A) ;
U36( SLV_CYC_DEC_N = Z)
= ND4( DB_ACTIVE_DLY1_N = A, REQA = B, DB_ACTIVE = C
, U32.Z = D) ;
U200( U200.Z = Z)
= IV( U41.SLV_BGACK = A) ;
U101( U101.Z = Z)
= NR2( WR_N = B, REQA = A) ;
U100( WR_N = Z)
= IV( U55.QN = A) ;
U900( SLV_SEL = Z)
= ND2( TP2-9 = B, SLV_REG_DEC_N = A) ;
U902( TP1-9 = Z)
= IV( U901.Z = A) ;
U901( U901.Z = Z)
= IV( SLV_REG_DEC_N = A) ;
U55( SLV_RD__WR_N = Q, U55.QN = QN)
= FJK2( RESET_N = CD, DB_CLK = CP, ACK_RD = J
, CYC_DEC = K) ;
U18( U18.Z = Z)
= IV( U17.QN = A) ;
U53( INH_OR_RESET_N = Z)
= IV( U52.Z = A) ;
U52( U52.Z = Z)
= ND2( U12.Z = B, RESET_N = A) ;
U12( U12.Z = Z)
= IV( DEV_INH = A) ;
U051( CLR_SLV_N = Z)
= IVP( U50.Z = A) ;
U50( U50.Z = Z)
= ND2( RESET_N = B, U49.QN = A) ;
U49( U49.QN = QN)
= FD1( U48.Z = D, DB_CLK = CP) ;
U48( U48.Z = Z)
= ND2( U47.Z = B, U46.Z = A) ;
U47( U47.Z = Z)
= ND3( READCYC = C, DEV_REQ_N = B, SLVACK = A) ;
U46( U46.Z = Z)
= ND3( SLV_BSY_N = A, DEV_REQ_N = C, SLVACK = B) ;
U44( U44.Z = Z)
= IV( RESET_N = A) ;
U43( SW_RES_PLS_N = SW_RES_PLS_N)
= SW_RES_PULSE( DB_CLK = DB_CLK, SW_RES_N = SW_RES_N, U44.Z = RESET) ;
U40( U40.Z = Z)
= IV( BIT_16_MODE_N = A) ;
U16( CYC_DEC = Z)
= IV( SLV_CYC_DEC_N = A) ;
U29( SLV_WRLAT_ENBL_N = Q)
= FD2S( RESET_N = CD, DB_CLK = CP, ACK_WR = TE
, DEV_REQ_N = TI, NC/1/ = D) ;
U42( SLV_SRC_SEL_N-5 = SLV_SRC_SEL_N-5, SLV_SRC_SEL_N-4 = SLV_SRC_SEL_N-4, SLV_SRC_SEL_N-3 = SLV_SRC_SEL_N-3
, SLV_SRC_SEL_N-2 = SLV_SRC_SEL_N-2, SLV_SRC_SEL_N-1 = SLV_SRC_SEL_N-1, SLV_SRC_SEL_N-0 = SLV_SRC_SEL_N-0
, REGSEL_LAT_N = REGSEL_LAT_N)
= SLAVE_SRC( MSTR_REQ_N = MSTR_REQ_N, 32_BIT_N = 32_BIT_N, RESET_N = RESET_N
, DB_CLK = DB_CLK, DB_AD_LAT-19 = DB_AD_LAT-19, STAT_ADDR_N = STAT_ADDR_N
, BIT_16_MODE_N = BIT_16_MODE_N, REQA = DEV_REQ, SLV_CYC_DEC_N = SLV_CYC_DEC_N
, INT_SLV_DEV_ACK_N = INT_SLV_ACK_N, SLV_REG_DEC_N = SLV_REG_DEC_N) ;
U30( SLV_DRV_DB_N = Z)
= ND2( REQA = B, READCYC = A) ;
U24( TP1-5 = Z)
= IV( U23.Z = A) ;
U23( U23.Z = Z)
= IV( INT_BGACK_N = A) ;
U39( SLV_ACT = Z)
= ND4( MSTR_REQ_N = C, SLV_BSY_N = B, U32.Z = D
, DB_BUSY_N = A) ;
U21( U21.Z = Z)
= IV( U04.Q = A) ;
U26( DEV_REQ_N = Z)
= IVP( DEV_REQ = A) ;
U32( U32.Z = Z)
= IV( INT_ACK = A) ;
U11( U11.Z = Z)
= IV( DB_WR = A) ;
U05( DB_CLK = Z)
= B2A( DB_CLK_N = A) ;
U13( RESET_N = Z)
= IVP( RESET = A) ;
U25( BGACK_N = Z)
= B1( U200.Z = A) ;
U22( BRQ_N = Z)
= B1( U21.Z = A) ;
U07( EN_SLV_ACK_OUT_N = QN)
= FJK2S( DB_CLK = CP, SLV_SEL = TI, INH_OR_RESET_N = CD
, INT_SLV_DEV_ACK_N = K, CYC_DEC = TE, NC/0/ = J) ;
U14( U14.Z = Z)
= ND2( SLV_BSY_N = B, U11.Z = A) ;
U28( REQA = Z)
= IVP( DEV_REQ_N = A) ;
U15( ACK_RD = Z)
= NR2( INT_SLV_DEV_ACK_N = B, U14.Z = A) ;
U34( DB_ACTIVE = Q)
= FJK2( RESET_N = CD, DB_CLK = CP, DB_ACT_DETECT = J
, DEV_REQ_N = K) ;
U35( DB_BUSY_N = QN)
= FJK2( RESET_N = CD, DB_CLK = CP, DB_BSY_DETECT = J
, DEV_REQ_N = K) ;
U33( DB_BSY_DETECT = Z)
= NR2( U32.Z = B, DEV_REQ_N = A) ;
U19( INT_BGACK = Z)
= IV( INT_BGACK_N = A) ;
U41( 32_BIT_N = 32_BIT_N, SLV_BSY_N = SLV_BSY_N, INT_BGACK_N = INT_BGACK_N
, CLR_DEV_ACK = CLR_DEV_ACK, U41.SLV_BGACK = SLV_BGACK, SLV_RDLAT_ENBL_N-0 = SLV_RDLAT_ENBL_N-0
, SLV_RDLAT_ENBL_N-1 = SLV_RDLAT_ENBL_N-1, SLV_REG_ACC_N = SLV_REG_ACC_N, SLV_WR_CYC_N = SLV_WR_CYC_N
, SLV_AS_N = SLV_AS_N, EN_CPU_DTA_BUS_N-0 = EN_CPU_DTA_BUS_N-0, EN_CPU_DTA_BUS_N-1 = EN_CPU_DTA_BUS_N-1
, EN_CPU_ADDR_BUS = EN_CPU_ADDR_BUS)
= SLAVE_SQNCR( REGSEL_LAT_N = REGSEL_LAT_N, RESET_N = RESET_N, DB_CLK = DB_CLK
, U40.Z = BIT_16_MODE, SLV_DATA_VALID = SLV_DTA_VALID, SLV_WRLAT_ENBL_N = SLV_WRLAT_ENBL_N
, U52.Z = RST_OR_INH, INT_SLV_DEV_ACK_N = INT_DEV_ACK_N, DEV_REQ_N = DEV_REQ_N
, CLR_SLV_N = CLR_SLV_N, INT_CPU_BRQ_N = INT_CPU_BRQ_N, CPU_AS = CPU_AS
, CPU_BG_N = CPU_BG_N, INT_DSACK-1 = INT_DSACK-1, INT_DSACK-0 = INT_DSACK-0
, U18.Z = SLV_RD__WR_N) ;
U38( SLV_DATA_VALID = Q)
= FJK2S( RESET_N = CD, DB_CLK = CP, SLV_BSY_N = TE
, U101.Z = J, NC/0/ = K, NC/0/ = TI) ;
U17( READCYC = Q, U17.QN = QN)
= FJK2( DB_CLK = CP, INH_OR_RESET_N = CD, ACK_RD = J
, DEV_REQ_N = K) ;
U20( INT_CPU_BRQ_N = Z)
= IV( U04.Q = A) ;
U10( INT_SLV_DEV_ACK_N = Z)
= IVP( SLVACK = A) ;
U37( DB_ACTIVE_DLY1_N = Q)
= FD1( U1201.Z = D, DB_CLK = CP) ;
U31( DB_ACT_DETECT = Z)
= NR2( SLV_ACT = B, DEV_REQ_N = A) ;
U27( ACK_WR = Z)
= NR2( INT_SLV_DEV_ACK_N = B, U11.Z = A) ;
U03( BUS_NEEDED = Z)
= ND2( TP2-9 = B, U02.Z = A) ;
U04( U04.Q = Q, TP1-2 = QN)
= FJK2S( DB_CLK = CP, CLR_SLV_N = CD, BUS_NEEDED = TI
, CYC_DEC = TE, NC/0/ = J, INT_BGACK = K) ;
U02( U02.Z = Z)
= ND2( U901.Z = B, STAT_ADDR_N = A) ;
U09( SLVACK = Q, SLV_ACK_OUT_N = QN)
= FJK2S( DB_CLK = CP, SLV_SEL = TI, CLR_SLV_N = CD
, CLR_DEV_ACK = K, CYC_DEC = TE, NC/0/ = J) ;
END MODULE ;
|