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140 | ###############################################################################
# Copyright (c) 2015-2024 by Altair Engineering, Inc.
# All rights reserved.
#
# Altair Engineering, Inc. makes this software available as part of the Vision
# tool platform. As long as you are a licensee of the Vision tool platform
# you may make copies of the software and modify it to be used within the
# Vision tool platform, but you must include all of this notice on any copy.
# Redistribution without written permission to any third party, with or
# without modification, is not permitted.
# Altair Engineering, Inc. does not warrant that this software is error free
# or fit for any purpose. Altair Engineering, Inc. disclaims any liability for
# all claims, expenses, losses, damages and costs any user may incur as a
# result of using, copying or modifying the software.
# =============================================================================
# @userware
# Configure Clocked Cells
# @section
# Analyze the Loaded Database
# @description
# Userware to flag cells as clocked cells and
# ports of clocked cells as the clock ports.
# @files
# configureClockedCells.tcl
# @example
# demo/verilog/gl85.v
# @cmdline
# -verilog @example[0]
# -userware @files[0]
# @tag
# zdb
###############################################################################
##
# List of glob style pattern to match clocked cells.
#
set _config(clockedCellPattern) {
"FD*"
}
##
# List of glob style pattern to match clocked ports.
#
set _config(clockedPortPattern) {
"CP"
}
# =============================================================================
# ConfigureClockedCells - Configure Clocked Cells.
# =============================================================================
#
proc ConfigureClockedCells {db} {
##
# Return if the database is empty.
#
if {$db == {}} {
return
}
##
# Loop over all cells and flag all clocked cells and ports.
#
$db foreach cell cell {
##
# Skip all cells not matching one of the clocked cell patterns.
#
if {![_flagClockedCell $db $cell]} {
continue
}
##
# Loop over all ports of this clocked cell and flag the clocked ports.
#
$db foreach port $cell port {
_flagClockedPort $db $port
}
}
}
# -----------------------------------------------------------------------------
# _flagClockedCell - Check if the given cell matches a clock cell pattern.
# -----------------------------------------------------------------------------
#
proc _flagClockedCell {db cell} {
global _config
##
# Get the name of the cell.
#
set cellname [$db oid oname $cell]
##
# Flag this cell if a pattern in _config(clockedCellPattern)
# matches the cell name.
#
foreach clockedCellPattern $_config(clockedCellPattern) {
if {[string match $clockedCellPattern $cellname]} {
$db flag $cell set clock
return true
}
}
return false
}
# -----------------------------------------------------------------------------
# _flagClockedPort - Check if the given port matches a clock port pattern.
# -----------------------------------------------------------------------------
#
proc _flagClockedPort {db port} {
global _config
##
# Get the name of the port.
#
set portName [$db oid oname $port]
##
# Flag this port if a pattern in _config(clockedPortPattern)
# matches the port name.
#
foreach clockedPortPattern $_config(clockedPortPattern) {
if {[string match $clockedPortPattern $portName]} {
$db flag $port set clock
}
}
}
##
# Use gui database runOrRegisterChangedCallback to immediately run
# ConfigureClockedCells
# if we have a database, or otherwise register the proc to be executed after
# the database is available.
#
gui database runOrRegisterChangedCallback ConfigureClockedCells
|