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413 | module REGPAD(B8BO_A, B8BO_B, B8BO, B8BIN_A, B8BIN_B, B8BIN, SEL16, SEL_CTRN,
WRB, WRC, WRBC, BOUT, COUT, BCOUT, RESETPC, WRH, WRL, WRHL, WRD,
WRE, WRDE, HOUT, LOUT, HLOUT, DOUT, EOUT, DEOUT, ID19, ID13, ID3,
LOADCTRALL_NOT, CTROUTEN, EXTRA_IN, INCR, DECR, CLK, LATCHCLK, T4);
output [7:0] B8BO_A;
output [7:0] B8BO_B;
output [7:0] B8BO;
input [7:0] B8BIN_A;
input [7:0] B8BIN_B;
input [7:0] B8BIN;
input EXTRA_IN;
input SEL16;
input SEL_CTRN;
input WRB;
input WRC;
input WRBC;
input BOUT;
input COUT;
input BCOUT;
input RESETPC;
input WRH;
input WRL;
input WRHL;
input WRD;
input WRE;
input WRDE;
input HOUT;
input LOUT;
input HLOUT;
input DOUT;
input EOUT;
input DEOUT;
input ID19;
input ID13;
input ID3;
input LOADCTRALL_NOT;
input CTROUTEN;
input INCR;
input DECR;
input CLK;
input LATCHCLK;
input T4;
supply1 VCC;
wire [7:0] M8A;
wire [7:0] M8B;
wire [7:0] W8A;
wire [7:0] W8B;
wire [7:0] DN8_A;
wire [7:0] DN8_B;
wire [7:0] DDN8A;
wire [7:0] DDN8B;
wire [7:0] QB8A;
wire [7:0] QB8B;
wire [7:0] QD8A;
wire [7:0] QD8B;
wire [7:0] QP8A;
wire [7:0] QP8B;
wire [7:0] QS8A;
wire [7:0] QS8B;
wire [7:0] QH8A;
wire [7:0] QH8B;
wire [7:0] QW8A;
wire [7:0] QW8B;
wire XCHG;
wire LOADCTRALL;
wire CLKBAR;
and #(1 ,1 ) X0 (DDN8A[0], B8BIN_A[0], SEL_CTRN);
and #(1 ,1 ) X1 (DDN8A[1], B8BIN_A[1], SEL_CTRN);
and #(1 ,1 ) X2 (DDN8A[2], B8BIN_A[2], SEL_CTRN);
and #(1 ,1 ) X3 (DDN8A[3], B8BIN_A[3], SEL_CTRN);
and #(1 ,1 ) X4 (DDN8A[4], B8BIN_A[4], SEL_CTRN);
and #(1 ,1 ) X5 (DDN8A[5], B8BIN_A[5], SEL_CTRN);
and #(1 ,1 ) X6 (DDN8A[6], B8BIN_A[6], SEL_CTRN);
and #(1 ,1 ) X7 (DDN8A[7], B8BIN_A[7], SEL_CTRN);
and #(1 ,1 ) X8 (DDN8B[0], B8BIN_B[0], SEL_CTRN);
and #(1 ,1 ) X9 (DDN8B[1], B8BIN_B[1], SEL_CTRN);
and #(1 ,1 ) X10 (DDN8B[2], B8BIN_B[2], SEL_CTRN);
and #(1 ,1 ) X11 (DDN8B[3], B8BIN_B[3], SEL_CTRN);
and #(1 ,1 ) X12 (DDN8B[4], B8BIN_B[4], SEL_CTRN);
and #(1 ,1 ) X13 (DDN8B[5], B8BIN_B[5], SEL_CTRN);
and #(1 ,1 ) X14 (DDN8B[6], B8BIN_B[6], SEL_CTRN);
and #(1 ,1 ) X15 (DDN8B[7], B8BIN_B[7], SEL_CTRN);
REGPAIRS BC (QB8A, QB8B, DN8_A, DN8_B, VCC, WRC, WRB, WRBC, CLK);
REGPAIRS DE (QD8A, QD8B, DN8_A, DN8_B, VCC, WRE, WRD, WRDE, CLK);
REGPAIRS HL (QH8A, QH8B, M8A, M8B, VCC, WRL, WRH, WRHL, CLK);
G16BCTR G16CTR (B8BO_A, B8BO_B, DDN8A, DDN8B, LATCHCLK, LOADCTRALL,
CTROUTEN, INCR, DECR, RESETPC);
OCNAND V3 (B8BO_A, QB8A, BCOUT);
OCNAND V7 (B8BO, QB8A, COUT);
OCNAND V8 (B8BO, QB8B, BOUT);
OCNAND W6 (B8BO_A, QH8A,HLOUT);
OCNAND W10 (B8BO, QH8A, LOUT);
OCNAND W11 (B8BO, QH8B, HOUT);
OCNAND W8 (B8BO_A, QD8A, DEOUT);
OCNAND W12 (B8BO, QD8A, EOUT);
OCNAND W13 (B8BO, QD8B, DOUT);
not #(1 ,1 ) U5 (LOADCTRALL, LOADCTRALL_NOT);
nor #(1 ,1 ) W17 (XCHG, T4, ID19, ID3, ID13);
MUXPAIRS U1 (DN8_A, B8BIN, B8BIN_A, SEL16);
MUXPAIRS U2 (DN8_B, B8BIN, B8BIN_B, SEL16);
MUXPAIRS W1 (M8A,DN8_A, QD8A, XCHG);
MUXPAIRS W2 (M8B,DN8_B, QD8B, XCHG);
endmodule
module G16BCTR(OUT8A, OUT8B, D8A, D8B, CLK, LOADALL, OUTEN, INCR, DECR, RESET);
output [7:0] OUT8A;
output [7:0] OUT8B;
input [7:0] D8A;
input [7:0] D8B;
input CLK;
input LOADALL;
input OUTEN;
input INCR;
input DECR;
input RESET;
wire NET0;
wire NET1;
wire NET3;
wire NET6;
wire NET9;
wire NET12;
wire [7:0] Q8A;
wire [7:0] Q8B;
wire RC1;
wire RC2;
wire RC3;
nor #(1 ,1 ) U0 (NET0, INCR, DECR);
not #(1 ,1 ) U1 (NET1, DECR);
and #(1 ,1 ) U3 (NET3, LOADALL, RESET);
G4BCTR U4 (Q8A[3], Q8A[2], Q8A[1], Q8A[0], RC1, D8A[3], D8A[2], D8A[1],
D8A[0], CLK, NET1, NET3, NET0, NET0);
and #(1 ,1 ) U6 (NET6, NC_3, RESET);
G4BCTR U7 (Q8A[7], Q8A[6], Q8A[5], Q8A[4], RC2, D8A[7], D8A[6], D8A[5],
D8A[4], CLK, NET1, NET6, RC1, RC1);
and #(1 ,1 ) U9 (NET9, LOADALL, RESET);
G4BCTR U10 (Q8B[3], Q8B[2], Q8B[1], Q8B[0], RC3, D8B[3], D8B[2], D8B[1],
D8B[0], CLK, NET1, NET9, RC2, RC2);
and #(1 ,1 ) U12 (NET12, LOADALL, RESET);
G4BCTR U13 (Q8B[7], Q8B[6], Q8B[5], Q8B[4], , D8B[7], D8B[6], D8B[5],
D8B[4], CLK, NET1, NET12, RC3, RC3);
OCNAND U14 (OUT8A, Q8A, OUTEN);
OCNAND U15 (OUT8B, Q8B, OUTEN);
endmodule
module MUXPAIRS(Y8, A8, B8, SEL);
output [7:0] Y8;
input [7:0] A8;
inout [7:0] B8;
input SEL;
MUX4BIT U0 (Y8[0], Y8[1], Y8[2], Y8[3], A8[0], A8[1], A8[2], A8[3], B8[0],
B8[1], B8[2], B8[3], SEL);
MUX4BIT U1 (Y8[4], Y8[5], Y8[6], Y8[7], A8[4], A8[5], A8[6], A8[7], B8[4],
B8[5], B8[6], B8[7], SEL);
endmodule
module OCNAND(O8, I8, ENABLE);
output [7:0] O8;
input [7:0] I8;
input ENABLE;
notif1 #(2 ,2 ) U0 (O8[0], I8[0], ENABLE);
notif1 #(2 ,2 ) U1 (O8[1], I8[1], ENABLE);
notif1 #(2 ,2 ) U2 (O8[2], I8[2], ENABLE);
notif1 #(2 ,2 ) U3 (O8[3], I8[3], ENABLE);
notif1 #(2 ,2 ) U4 (O8[4], I8[4], ENABLE);
notif1 #(2 ,2 ) U5 (O8[5], I8[5], ENABLE);
notif1 #(2 ,2 ) U6 (O8[6], I8[6], ENABLE);
notif1 #(2 ,2 ) U7 (O8[7], I8[7], ENABLE);
endmodule
module REGPAIRS(Q8_A, Q8_B, D8_A, D8_B, CLEAR, WRLOW, WRHIGH, WRBOTH, CK);
output [7:0] Q8_A;
output [7:0] Q8_B;
input [7:0] D8_A;
input [7:0] D8_B;
input CLEAR;
supply1 VCC;
input WRLOW;
input WRHIGH;
input WRBOTH;
input CK;
wire WRENABLE0;
wire WRENABLE1;
REG8BITS U0 (Q8_A, D8_A, CK, WRENABLE0, CLEAR, VCC);
REG8BITS U1 (Q8_B, D8_B, CK, WRENABLE1, CLEAR, VCC);
or #(1 ,1 ) U2 (WRENABLE0, WRLOW, WRBOTH);
or #(1 ,1 ) U3 (WRENABLE1, WRHIGH, WRBOTH);
endmodule
module G4BCTR(QD, QC, QB, QA, CARRY, DATAD, DATAC, DATAB, DATAA, CLK, UD, LOAD,
ENP, ENT);
output QD;
output QC;
output QB;
output QA;
output CARRY;
input DATAD;
input DATAC;
input DATAB;
input DATAA;
input CLK;
input UD;
input LOAD;
output ENP;
input ENT;
supply1 VCC;
wire N2;
wire N3;
wire N4;
wire N5;
wire N6;
wire N7;
wire N8;
wire N9;
wire N10;
wire N11;
wire N12;
wire N13;
wire N14;
wire N15;
wire N16;
wire N17;
wire N18;
wire N19;
wire N20;
wire N21;
wire N22;
wire N23;
wire N24;
wire N25;
wire N26;
wire N27;
wire N29;
wire N30;
wire N31;
wire N32;
wire N33;
wire N34;
wire N35;
wire N36;
wire N37;
wire N38;
wire N39;
wire N40;
wire N41;
wire N42;
wire N43;
wire N44;
wire QABAR;
wire QBBAR;
wire QCBAR;
wire QDBAR;
wire QA_BUF;
wire QB_BUF;
wire QC_BUF;
wire QD_BUF;
not #(1 ,1 ) U2 (N2, UD);
not #(1 ,1 ) U3 (N3, LOAD);
not #(1 ,1 ) U4 (N4, ENP);
not #(1 ,1 ) U5 (N5, ENT);
and #(1 ,1 ) U6 (N6, N3, DATAA);
and #(1 ,1 ) U7 (N7, N3, DATAB);
and #(1 ,1 ) U8 (N8, N3, DATAC);
and #(1 ,1 ) U9 (N9, N3, DATAD);
not #(1 ,1 ) U10 (N10, N3);
and #(1 ,1 ) U11 (N11, N4, LOAD);
and #(1 ,1 ) U12 (N12, N2, QA_BUF);
not #(1 ,1 ) U13 (N13, N2);
and #(1 ,1 ) U14 (N14, N13, QABAR);
nor #(1 ,1 ) U15 (N15, N12, N14);
and #(1 ,1 ) U16 (N16, N2, QB_BUF);
not #(1 ,1 ) U17 (N17, N2);
and #(1 ,1 ) U18 (N18, N17, QBBAR);
nor #(1 ,1 ) U19 (N19, N16, N18);
and #(1 ,1 ) U20 (N20, N2, QC_BUF);
not #(1 ,1 ) U21 (N21, N2);
and #(1 ,1 ) U22 (N22, N21, QCBAR);
nor #(1 ,1 ) U23 (N23, N20, N22);
and #(1 ,1 ) U24 (N24, N2, QD_BUF);
not #(1 ,1 ) U25 (N25, N2);
and #(1 ,1 ) U26 (N26, N25, QDBAR);
nor #(1 ,1 ) U27 (N27, N24, N26);
nand #(1 ,1 ) U28 (CARRY, N5, N15, N19, N23, N27);
not #(1 ,1 ) U29 (N29, N11);
nand #(1 ,1 ) U30 (N30, N15, N11);
nand #(1 ,1 ) U31 (N31, N15, N11, N19);
nand #(1 ,1 ) U32 (N32, N15, N11, N19, N23);
and #(1 ,1 ) U33 (N33, QA_BUF, N29, N10);
and #(1 ,1 ) U34 (N34, QABAR, N11);
and #(1 ,1 ) U35 (N35, QB_BUF, N30, N10);
and #(1 ,1 ) U36 (N36, QBBAR, N11, N15);
and #(1 ,1 ) U37 (N37, QC_BUF, N31, N10);
and #(1 ,1 ) U38 (N38, QCBAR, N11, N15, N19);
and #(1 ,1 ) U39 (N39, QD_BUF, N32, N10);
and #(1 ,1 ) U40 (N40, QDBAR, N11, N15, N19, N23);
or #(1 ,1 ) U41 (N41, N33, N34, N6);
or #(1 ,1 ) U42 (N42, N35, N36, N8);
or #(1 ,1 ) U43 (N43, N37, N38, N7);
or #(1 ,1 ) U44 (N44, N39, N40, N9);
DFF U45 (QA_BUF, N41, CLK, VCC, VCC);
buf U45B (QA, QA_BUF);
not U45A (QABAR, QA_BUF);
DFF U46 (QB_BUF, N42, CLK, VCC, VCC);
buf U46B (QB, QB_BUF);
not U46A (QBBAR, QB_BUF);
DFF U47 (QC_BUF, N43, CLK, VCC, VCC);
buf U47B (QC, QC_BUF);
not U47A (QCBAR, QC_BUF);
DFF U48 (QD_BUF, N44, CLK, VCC, VCC);
buf U48B (QD, QD_BUF);
not U48A (QDBAR, QD_BUF);
endmodule
module MUX4BIT(Y0, Y1, Y2, Y3, A0, A1, A2, A3, B0, B1, B2, B3, SEL);
output Y0;
output Y1;
output Y2;
output Y3;
input A0;
input A1;
input A2;
input A3;
input B0;
input B1;
input B2;
input B3;
input SEL;
wire CHOOSE_BUF;
wire CHOOSE_NOT;
wire PICK_A1;
wire PICK_B1;
wire A5;
wire A6;
wire A7;
wire A8;
wire A9;
wire A10;
not #(2 ,2 ) U1 (CHOOSE_NOT, SEL);
not #(2 ,2 ) U2 (CHOOSE_BUF, CHOOSE_NOT);
and #(2 ,2 ) U3 (PICK_A1, CHOOSE_NOT, A0);
and #(2 ,2 ) U4 (PICK_B1, CHOOSE_BUF, B0);
and #(2 ,2 ) U5 (A5, CHOOSE_NOT, A1);
and #(2 ,2 ) U6 (A6, CHOOSE_BUF, B1);
and #(2 ,2 ) U7 (A7, CHOOSE_NOT, A2);
and #(2 ,2 ) U8 (A8, CHOOSE_BUF, B2);
and #(2 ,2 ) U9 (A9, CHOOSE_NOT, A3);
and #(2 ,2 ) U10 (A10, CHOOSE_BUF, B3);
or #(2 ,2 ) U11 (Y0, PICK_A1, PICK_B1);
or #(2 ,2 ) U12 (Y1, A5, A6);
or #(2 ,2 ) U13 (Y2, A7, A8);
or #(2 ,2 ) U14 (Y3, A9, A10);
endmodule
module REG8BITS(L8, D8, CK, WRENABLE, CLEAR, PRESET);
output [7:0] L8;
input [7:0] D8;
input CK;
input WRENABLE;
input CLEAR;
input PRESET;
wire REG_IN0;
wire REG_IN1;
wire REG_IN2;
wire REG_IN3;
wire REG_IN4;
wire REG_IN5;
wire REG_IN6;
wire REG_IN7;
DFF R0 (L8[0], REG_IN0, CK, PRESET, CLEAR);
DFF R1 (L8[1], REG_IN1, CK, PRESET, CLEAR);
DFF R2 (L8[2], REG_IN2, CK, PRESET, CLEAR);
DFF R3 (L8[3], REG_IN3, CK, PRESET, CLEAR);
DFF R4 (L8[4], REG_IN4, CK, PRESET, CLEAR);
DFF R5 (L8[5], REG_IN5, CK, PRESET, CLEAR);
DFF R6 (L8[6], REG_IN6, CK, PRESET, CLEAR);
DFF R7 (L8[7], REG_IN7, CK, PRESET, CLEAR);
MUX2TO1 U20 (REG_IN0, WRENABLE, L8[0], D8[0]);
MUX2TO1 U21 (REG_IN1, WRENABLE, L8[1], D8[1]);
MUX2TO1 U22 (REG_IN2, WRENABLE, L8[2], D8[2]);
MUX2TO1 U23 (REG_IN3, WRENABLE, L8[3], D8[3]);
MUX2TO1 U24 (REG_IN4, WRENABLE, L8[4], D8[4]);
MUX2TO1 U25 (REG_IN5, WRENABLE, L8[5], D8[5]);
MUX2TO1 U26 (REG_IN6, WRENABLE, L8[6], D8[6]);
MUX2TO1 U27 (REG_IN7, WRENABLE, L8[7], D8[7]);
endmodule
module MUX2TO1(Z, SEL, D0, D1);
output Z;
input SEL;
input D0;
input D1;
wire L2;
wire L3;
wire L5;
wire L6;
or #(1 ,1 ) G1 (Z, L2, L3);
and #(1 ,1 ) G2 (L2, L5, D0);
and #(1 ,1 ) G3 (L3, L6, D1);
not #(1 ,1 ) G5 (L5, SEL);
buf #(1 ,1 ) G6 (L6, SEL);
endmodule
module EXTRA_A_MODULE(Y, D0, D1);
output Y;
input D0;
input D1;
and #(1 ,1 ) U1 (Y, D0, D1);
endmodule
primitive DFF(Q, D, CK, SET, CLR);
output Q;
input D, CK, SET, CLR;
endprimitive
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