Variables of the same name share signals. For example, in the diagram below, the variable j is used in three locations:
The variable j in the upper part of the diagram is the declared variable. Only declared variables are allowed input signals. In addition, there can be only one declared variable of a given name. The other two j variables are referenced variables. Wires cannot be fed directly into referenced variables; they receive their input from the declared variable.
All variables can have any number of output signals.