This block takes the value of the D-input at a specific cycle of the clock, such as the rising edge, when the clear option is off. This value becomes the Q output. At other times, the Q output remains unchanged.


When the E/C port of the block is 0, the D input has no effect on the outputs. When The E/C is high, the Q output is equal to D.


The JK Flip Flop works on a definite portion of the clock cycle (such as the rising edge of the clock). The combination J=0 K=0 holds the state, the combination J=1 K=0 sets the state, the combination J=0 K=1 resets the state, the combination J=1 K=1 toggles the state.


This block sets its output when the S port is high and R is low, resets its output when the R port is high and S port is low, !Q is the complement of Q. While both S and R are low, the SR Flip Flop maintains the Q and the !Q outputs in a constant state. If both S and R are high, Q and !Q are both low.